1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Universal Serial Communication Interface B1 SPI 2xx
16 */
17 metaonly module USCI_B1_SPI_2xx inherits IUSCI_B1_SPI {
18 19 20
21 create(IClock.Instance clock);
22
23 /*! USCI_B1 transmit interrupt enable */
24 enum UCB1TXIE_t {
25 UCB1TXIE_OFF = 0x00, /*! Interrupt disabled */
26 UCB1TXIE = 0x08 /*! Interrupt enabled */
27 };
28
29 /*! USCI_B1 receive interrupt enable */
30 enum UCB1RXIE_t {
31 UCB1RXIE_OFF = 0x00, /*! Interrupt disabled */
32 UCB1RXIE = 0x04 /*! Interrupt enabled */
33 };
34
35 /*! USCI_xx SPI Interrupt Enable Register */
36 struct UC1IE_t {
37 UCB1TXIE_t UCB1TXIE; /*! USCI_B1 transmit interrupt enable
38 * 0 Interrupt disabled
39 * 1 Interrupt enabled */
40 UCB1RXIE_t UCB1RXIE; /*! USCI_B1 receive interrupt enable
41 * 0 Interrupt disabled
42 * 1 Interrupt enabled */
43 }
44
45 instance:
46 /*! @_nodoc */
47 config IClock.Instance clock;
48
49 /*! USCI_B1 Interrupt Enable Register */
50 config UC1IE_t UC1IE = {
51 UCB1TXIE : UCB1TXIE_OFF,
52 UCB1RXIE : UCB1RXIE_OFF
53 };
54
55 /*! USCI_A1 SPI interrupt enables */
56 config regIntVect_t interruptSource[2];
57
58 /*! Determine if each Register needs to be forced set or not */
59 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
60 [
61 { register : "UCB1CTL0" , regForceSet : false },
62 { register : "UCB1CTL1" , regForceSet : false },
63 { register : "UCB1BR0" , regForceSet : false },
64 { register : "UCB1BR1" , regForceSet : false },
65 { register : "UCB1STAT" , regForceSet : false },
66 { register : "UCB1RXBUF" , regForceSet : false },
67 { register : "UCB1TXBUF" , regForceSet : false },
68 { register : "UC1IE" , regForceSet : false }
69 ];
70 }