1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2008 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     * 
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     * 
    11     * --/COPYRIGHT--*/
    12    /*!
    13     * Universal Serial Communication Interface A0 UART 2xx
    14     */
    15    metaonly interface IUSCI_A0_UART inherits IUSCI_UART {
    16    
    17    instance:
    18        /*! Control Register 0 */
    19        config UCxCTL0_t UCA0CTL0 = {
    20            UCPEN       : UCPEN_OFF,
    21            UCPAR       : UCPAR_OFF,
    22            UCMSB       : UCMSB_OFF,
    23            UC7BIT      : UC7BIT_OFF,
    24            UCSPB       : UCSPB_OFF,
    25            UCMODE      : UCMODE_0,
    26            UCSYNC      : UCSYNC_OFF,
    27        };
    28        
    29        /*! Control Register 1 */
    30        config UCxCTL1_t UCA0CTL1 = {
    31            UCSSEL      : UCSSEL_0,
    32            UCRXEIE     : UCRXEIE_OFF,
    33            UCBRKIE     : UCBRKIE_OFF,
    34            UCDORM      : UCDORM_OFF,
    35            UCTXADDR    : UCTXADDR_OFF,
    36            UCTXBRK     : UCTXBRK_OFF,
    37            UCSWRST     : UCSWRST,
    38        };
    39    
    40        /*! Modulation Control Register */
    41        config UCxMCTL_t UCA0MCTL = {
    42            UCBRF       : UCBRF_0,
    43            UCBRS       : UCBRS_0,
    44            UCOS16      : UCOS16_OFF,
    45        };
    46        
    47        /*! Status Register */
    48        config UCxSTAT_t UCA0STAT = {
    49            UCLISTEN    : UCLISTEN_OFF,
    50            UCFE        : UCFE_OFF,
    51            UCOE        : UCOE_OFF,
    52            UCPE        : UCPE_OFF,
    53            UCBRK       : UCBRK_OFF,
    54            UCRXERR     : UCRXERR_OFF,
    55            UCADDR      : UCADDR_OFF,
    56            UCIDLE      : UCIDLE_OFF,
    57            UCBUSY      : UCBUSY,
    58        };
    59        
    60        /*! IrDA Transmit Control Register */
    61        config UCxIRTCTL_t UCA0IRTCTL = {
    62            UCIRTXPL5   : UCIRTXPL5_OFF,
    63            UCIRTXPL4   : UCIRTXPL4_OFF,
    64            UCIRTXPL3   : UCIRTXPL3_OFF,
    65            UCIRTXPL2   : UCIRTXPL2_OFF,
    66            UCIRTXPL1   : UCIRTXPL1_OFF,
    67            UCIRTXPL0   : UCIRTXPL0_OFF,
    68            UCIRTXCLK   : UCIRTXCLK_OFF,
    69            UCIREN      : UCIREN_OFF,
    70        };
    71        
    72        /*! IrDA Receive Control Register */
    73        config UCxIRRCTL_t UCA0IRRCTL = {
    74            UCIRRXFL5   : UCIRRXFL5_OFF,
    75            UCIRRXFL4   : UCIRRXFL4_OFF,
    76            UCIRRXFL3   : UCIRRXFL3_OFF,
    77            UCIRRXFL2   : UCIRRXFL2_OFF,
    78            UCIRRXFL1   : UCIRRXFL1_OFF,
    79            UCIRRXFL0   : UCIRRXFL0_OFF,
    80            UCIRRXPL    : UCIRRXPL_OFF,
    81            UCIRRXFE    : UCIRRXFE_OFF,
    82        };
    83    
    84        /*! Auto Baud Rate Control Register */
    85        config UCxABCTL_t UCA0ABCTL = {
    86            UCDELIM1    : UCDELIM1_OFF,
    87            UCDELIM0    : UCDELIM0_OFF,
    88            UCSTOE      : UCSTOE_OFF,
    89            UCBTOE      : UCBTOE_OFF,
    90            UCABDEN     : UCABDEN_OFF,
    91        };
    92        
    93        /*! Receive Buffer Register */
    94        config Bits8 UCA0RXBUF = 0;
    95        
    96        /*! Transmit Buffer Register */
    97        config Bits8 UCA0TXBUF = 0;
    98        
    99        /*! Baud rate control register 0 */
   100        config Bits8 UCA0BR0 = 0;
   101        
   102        /*! Baud rate control register 1 */
   103        config Bits8 UCA0BR1 = 0;
   104    }