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13 14 15 16
17
18 package ti.catalog.c6000;
19
20 metaonly module TMS320C6654 inherits ti.catalog.ICpuDataSheet
21 {
22 config long cacheSizeL1[string] = [
23 ["0k", 0x0000],
24 ["4k", 0x1000],
25 ["8k", 0x2000],
26 ["16k", 0x4000],
27 ["32k", 0x8000],
28 ];
29
30 config long cacheSizeL2[string] = [
31 ["0k", 0x000000],
32 ["32k", 0x008000],
33 ["64k", 0x010000],
34 ["128k", 0x020000],
35 ["256k", 0x040000],
36 ["512k", 0x080000],
37 ["1024k", 0x100000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode', {
42 desc:"L1P Cache",
43 base: 0x00E00000,
44 map : [
45 ["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]
50 ],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"
53 }],
54 ['l1DMode', {
55 desc:"L1D Cache",
56 base: 0x00F00000,
57 map : [
58 ["0k",0x0000],
59 ["4k",0x1000],
60 ["8k",0x2000],
61 ["16k",0x4000],
62 ["32k",0x8000]
63 ],
64 defaultValue: "32k",
65 memorySection: "L1DSRAM"
66 }],
67 ['l2Mode', {
68 desc:"L2 Cache",
69 base: 0x00800000,
70 map : [
71 ["0k",0x0000],
72 ["32k",0x8000],
73 ["64k",0x10000],
74 ["128k",0x020000],
75 ["256k",0x040000],
76 ["512k",0x080000],
77 ["1024k", 0x100000]
78 ],
79 defaultValue: "0k",
80 memorySection: "L2SRAM"
81 }],
82 ];
83
84 instance:
85
86 override config string cpuCore = "6600";
87 override config string isa = "66";
88 override config string cpuCoreRevision = "1.0";
89
90 override config int minProgUnitSize = 1;
91 override config int minDataUnitSize = 1;
92 override config int dataWordSize = 4;
93
94 /*!
95 * ======== memMap ========
96 * The default memory map for this device
97 */
98 config xdc.platform.IPlatform.Memory memMap[string] = [
99 ["L2SRAM", {
100 comment: "1MB L2 SRAM/CACHE",
101 name: "L2SRAM",
102 base: 0x00800000,
103 len: 0x00100000,
104 space: "code/data",
105 access: "RWX"
106 }],
107
108 ["L1PSRAM", {
109 comment: "32KB RAM/CACHE L1 program memory",
110 name: "L1PSRAM",
111 base: 0x00E00000,
112 len: 0x00008000,
113 space: "code",
114 access: "RWX"
115 }],
116
117 ["L1DSRAM", {
118 comment: "32KB RAM/CACHE L1 data memory",
119 name: "L1DSRAM",
120 base: 0x00F00000,
121 len: 0x00008000,
122 space: "data",
123 access: "RW"
124 }],
125 ];
126 };
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130