1    /*
     2     *  Copyright (c) 2012 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITI8168.xdc ========
    15     *
    16     */
    17    package ti.catalog.c6000;
    18    
    19    /*!
    20     *  ======== ITI8168 ========
    21     *  An interface implemented by all TI8168 devices
    22     *
    23     *  This interface is defined to factor common data about all TI8168 type devices
    24     *  into a single place; they all have the same internal memory.
    25     */
    26    metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet
    27    {
    28    
    29        config long cacheSizeL1[string] = [
    30            ["0k",  0x0000],
    31            ["4k",  0x1000],
    32            ["8k",  0x2000],
    33            ["16k", 0x4000],
    34            ["32k", 0x8000],
    35        ];
    36    
    37        config long cacheSizeL2[string] = [
    38            ["0k",   0x00000],
    39            ["32k",  0x08000],
    40            ["64k",  0x10000],
    41            ["128k", 0x20000],
    42            ["256k", 0x40000],
    43        ];
    44    
    45        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    46                 ['l1PMode', {desc: "L1P Cache",
    47                             base: 0x10E00000,
    48                             map : [["0k",  0x0000],
    49                                    ["4k",  0x1000],
    50                                    ["8k",  0x2000],
    51                                    ["16k", 0x4000],
    52                                    ["32k", 0x8000]],
    53                             defaultValue: "32k",
    54                             memorySection: "L1PSRAM"}],
    55             
    56                     ['l1DMode', {desc: "L1D Cache",
    57                             base: 0x10F00000,
    58                             map : [["0k",  0x0000],
    59                                    ["4k",  0x1000],
    60                                    ["8k",  0x2000],
    61                                    ["16k", 0x4000],
    62                                    ["32k", 0x8000]],
    63                             defaultValue: "32k",
    64                             memorySection: "L1DSRAM"}],
    65                         
    66                 ['l2Mode', {desc: "L2 Cache",
    67                             base: 0x10800000,
    68                             map : [["0k",   0x00000],
    69                                    ["32k",  0x08000],
    70                                    ["64k",  0x10000],
    71                                    ["128k", 0x20000],
    72                                    ["256k", 0x40000]],
    73                             defaultValue: "0k",
    74                             memorySection: "IRAM"}], 
    75    
    76        ];
    77    
    78    instance:
    79        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    80        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
    81        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
    82    
    83        override config int     minProgUnitSize = 1;
    84        override config int     minDataUnitSize = 1;    
    85        override config int     dataWordSize    = 4;
    86    
    87        override config string   cpuCore        = "674";
    88        override config string   isa            = "674";
    89        override config string   cpuCoreRevision = "1.0";
    90    
    91        config xdc.platform.IPlatform.Memory memMap[string]  = [
    92    
    93            ["IRAM", {
    94                comment:    "Internal 256KB L2 memory",
    95                name:       "IRAM",
    96                base:       0x10800000,
    97                len:        0x40000,
    98                space:      "code/data",
    99                access:     "RWX"
   100            }],
   101            
   102            ["L1PSRAM", {
   103                comment:    "Internal 32KB L1 program memory",
   104                name:       "L1PSRAM",
   105                base:       0x10E00000,
   106                len:        0x8000,
   107                space:      "code",
   108                access:     "RWX"
   109            }],
   110    
   111            ["L1DSRAM", {
   112                comment:    "Internal 32KB L1 data memory",
   113                name:       "L1DSRAM",
   114                base:       0x10F00000,
   115                len:        0x8000,
   116                space:      "data",
   117                access:     "RW"
   118            }],
   119            
   120            ["OCMC_0", {
   121                comment:    "OCMC (On-chip RAM) Bank 0 (256KB)",
   122                name:       "OCMC_0",
   123                base:       0x40300000, 
   124                len:        0x40000,
   125                space:      "code/data",
   126                access:     "RWX"
   127            }],
   128            
   129            ["OCMC_1", {
   130                comment:    "OCMC (On-chip RAM) Bank 1 (256KB)",
   131                name:       "OCMC_1",
   132                base:       0x40400000, 
   133                len:        0x40000,
   134                space:      "code/data",
   135                access:     "RWX"
   136            }],
   137        ];
   138    };
   139    /*
   140     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,399; 8-17-2012 22:13:33; /db/ztree/library/trees/platform/platform-n27x/src/
   141     */
   142