1 /*
2 * Copyright (c) 2012 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320F28065.xdc ========
15 */
16 package ti.catalog.c2800;
17
18 /*!
19 * ======== ITMS320F28065 ========
20 */
21 metaonly interface ITMS320F28065 inherits ITMS320C283xx
22 {
23 instance:
24 override config string cpuCoreRevision = "1.0";
25
26 /*!
27 * ======== memMap ========
28 * The default memory map for this device
29 */
30 config xdc.platform.IPlatform.Memory memMap[string] = [
31 ["MSARAM", {
32 comment: "On-Chip RAM Memory",
33 name: "MSARAM",
34 base: 0x0,
35 len: 0x800,
36 page: 0,
37 space: "code/data"
38 }],
39
40 ["PIEVECT", {
41 comment: "On-Chip PIEVECT RAM Memory",
42 name: "PIEVECT",
43 base: 0xD00,
44 len: 0x100,
45 page: 1,
46 space: "data"
47 }],
48
49 ["L03DPSARAM", {
50 comment: "L0-L3 DPSARAM (8K x 16)",
51 name: "L03DPSARAM",
52 base: 0x8000,
53 len: 0x2000,
54 page: 0,
55 space: "code/data"
56 }],
57
58 ["L4SARAM", {
59 comment: "L4 SARAM (8K x 16)",
60 name: "L4SARAM",
61 base: 0xA000,
62 len: 0x2000,
63 page: 0,
64 space: "code/data"
65 }],
66
67 /* L5-L8 DPSARAM had to be split on 0xFFFF, to allow stack allocation
68 * to L56DPSARAM and still be sure stack will stay below 0xFFFF.
69 */
70 ["L56DPSARAM", {
71 comment: "L5-L6 DPSARAM (16K x 16)",
72 name: "L56DPSARAM",
73 base: 0xC000,
74 len: 0x4000,
75 page: 0,
76 space: "code/data"
77 }],
78
79 ["L78DPSARAM", {
80 comment: "L7-L8 DPSARAM (16K x 16)",
81 name: "L78DPSARAM",
82 base: 0x10000,
83 len: 0x04000,
84 page: 0,
85 space: "code/data"
86 }],
87
88 ["OTP", {
89 comment: "1K X 16 OTP memory",
90 name: "OTP",
91 base: 0x3D7800,
92 len: 0x0003FA,
93 page: 0,
94 space: "code"
95 }],
96
97 ["FLASH", {
98 comment: "64K X 16 Flash memory",
99 name: "FLASH",
100 base: 0x3E8000,
101 len: 0x00FF80,
102 page: 0,
103 space: "code"
104 }],
105
106 ["BEGIN", {
107 comment: "FLASH boot entry point",
108 name: "BEGIN",
109 base: 0x3f7ff6,
110 len: 0x000002,
111 page: 0,
112 space: "code"
113 }],
114
115 ["BOOTROM", {
116 comment: "On-Chip Boot ROM",
117 name: "BOOTROM",
118 base: 0x3F8000,
119 len: 0x007FC0,
120 page: 0,
121 space: "code"
122 }],
123 ];
124 }
125 /*
126 * @(#) ti.catalog.c2800; 1, 0, 0, 0,401; 8-17-2012 22:13:25; /db/ztree/library/trees/platform/platform-n27x/src/
127 */
128