1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== Timer_B3 ========
14 * MSP430 Timer_B timer
15 */
16 metaonly module Timer_B3 inherits ITimer_B {
17
18 /*! TB3IV Definitions */
19 enum IVValues {
20 TBIV_NONE = 0x0000, /*! No Interrupt pending */
21 TBIV_TBCCR1 = 0x0002, /*! TBCCR1_CCIFG */
22 TBIV_TBCCR2 = 0x0004, /*! TBCCR2_CCIFG */
23 TBIV_6 = 0x0006, /*! Reserved */
24 TBIV_8 = 0x0008, /*! Reserved */
25 TBIV_TBIFG = 0x000A /*! TBIFG */
26 };
27
28 instance:
29 /*! TBCTL, Timer_B3 Control Register */
30 config TBCTL_t TBCTL = {
31 TBCLGRP : TBCLGRP_0,
32 CNTL : CNTL_0,
33 TBSSEL : TBSSEL_0,
34 ID : ID_0,
35 MC : MC_0,
36 TBCLR : TBCLR_OFF,
37 TBIE : TBIE_OFF,
38 TBIFG : TBIFG_OFF
39 };
40
41 /*! TBCCTL0, Capture/Compare Control Register 0 */
42 config TBCCTLx_t TBCCTL0 = {
43 CM : CM_0,
44 CCIS : CCIS_0,
45 SCS : SCS_OFF,
46 CLLD : CLLD_0,
47 CAP : CAP_OFF,
48 OUTMOD : OUTMOD_0,
49 CCIE : CCIE_OFF,
50 CCI : CCI_OFF,
51 OUT : OUT_OFF,
52 COV : COV_OFF,
53 CCIFG : CCIFG_OFF
54 };
55
56 /*! TBCCTL1, Capture/Compare Control Register 1 */
57 config TBCCTLx_t TBCCTL1 = {
58 CM : CM_0,
59 CCIS : CCIS_0,
60 SCS : SCS_OFF,
61 CLLD : CLLD_0,
62 CAP : CAP_OFF,
63 OUTMOD : OUTMOD_0,
64 CCIE : CCIE_OFF,
65 CCI : CCI_OFF,
66 OUT : OUT_OFF,
67 COV : COV_OFF,
68 CCIFG : CCIFG_OFF
69 };
70
71 /*! TBCCTL2, Capture/Compare Control Register 2 */
72 config TBCCTLx_t TBCCTL2 = {
73 CM : CM_0,
74 CCIS : CCIS_0,
75 SCS : SCS_OFF,
76 CLLD : CLLD_0,
77 CAP : CAP_OFF,
78 OUTMOD : OUTMOD_0,
79 CCIE : CCIE_OFF,
80 CCI : CCI_OFF,
81 OUT : OUT_OFF,
82 COV : COV_OFF,
83 CCIFG : CCIFG_OFF
84 };
85
86 /*! TBCCR0, Timer_B Capture/Compare Register 0 */
87 config Bits16 TBCCR0 = 0;
88 /*! TBCCR1, Timer_B Capture/Compare Register 1 */
89 config Bits16 TBCCR1 = 0;
90 /*! TBCCR2, Timer_B Capture/Compare Register 2 */
91 config Bits16 TBCCR2 = 0;
92
93 /*! Timer interrupt enables */
94 config regIntVect_t interruptSource[4];
95
96 /*! Determine if each Register needs to be forced set or not */
97 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
98 [
99 { register : "TBCTL" , regForceSet : false },
100 { register : "TBCCTL0" , regForceSet : false },
101 { register : "TBCCTL1" , regForceSet : false },
102 { register : "TBCCTL2" , regForceSet : false },
103 { register : "TBCCR0" , regForceSet : false },
104 { register : "TBCCR1" , regForceSet : false },
105 { register : "TBCCR2" , regForceSet : false }
106 ];
107 }