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12 /*!
13 * ======== Timer_A5 ========
14 * MSP430 Timer_A5 timer
15 */
16 metaonly module Timer_A5 inherits ITimer_A {
17
18 instance:
19
20 override config string name = "TimerA5";
21
22 /*! Timer A5 Control Register */
23 config TACTL_t TAxCTL = {
24 TASSEL : TASSEL_0,
25 ID : ID_0,
26 MC : MC_0,
27 TACLR : TACLR_OFF,
28 TAIE : TAIE_OFF,
29 TAIFG : TAIFG_OFF
30 };
31
32 /*! Capture/Compare Control 0 */
33 config TACCTLx_t TACCTL0 = {
34 CM : CM_0,
35 CCIS : CCIS_0,
36 SCS : SCS_OFF,
37 SCCI : SCCI_OFF,
38 CAP : CAP_OFF,
39 OUTMOD : OUTMOD_0,
40 CCIE : CCIE_OFF,
41 CCI : CCI_OFF,
42 OUT : OUT_OFF,
43 COV : COV_OFF,
44 CCIFG : CCIFG_OFF
45 };
46
47 /*! Capture/Compare Control 1 */
48 config TACCTLx_t TACCTL1 = {
49 CM : CM_0,
50 CCIS : CCIS_0,
51 SCS : SCS_OFF,
52 SCCI : SCCI_OFF,
53 CAP : CAP_OFF,
54 OUTMOD : OUTMOD_0,
55 CCIE : CCIE_OFF,
56 CCI : CCI_OFF,
57 OUT : OUT_OFF,
58 COV : COV_OFF,
59 CCIFG : CCIFG_OFF
60 };
61
62 /*! Capture/Compare Control 2 */
63 config TACCTLx_t TACCTL2 = {
64 CM : CM_0,
65 CCIS : CCIS_0,
66 SCS : SCS_OFF,
67 SCCI : SCCI_OFF,
68 CAP : CAP_OFF,
69 OUTMOD : OUTMOD_0,
70 CCIE : CCIE_OFF,
71 CCI : CCI_OFF,
72 OUT : OUT_OFF,
73 COV : COV_OFF,
74 CCIFG : CCIFG_OFF
75 };
76
77 /*! Capture/Compare Control 3 */
78 config TACCTLx_t TACCTL3 = {
79 CM : CM_0,
80 CCIS : CCIS_0,
81 SCS : SCS_OFF,
82 SCCI : SCCI_OFF,
83 CAP : CAP_OFF,
84 OUTMOD : OUTMOD_0,
85 CCIE : CCIE_OFF,
86 CCI : CCI_OFF,
87 OUT : OUT_OFF,
88 COV : COV_OFF,
89 CCIFG : CCIFG_OFF
90 };
91
92 /*! Capture/Compare Control 4 */
93 config TACCTLx_t TACCTL4 = {
94 CM : CM_0,
95 CCIS : CCIS_0,
96 SCS : SCS_OFF,
97 SCCI : SCCI_OFF,
98 CAP : CAP_OFF,
99 OUTMOD : OUTMOD_0,
100 CCIE : CCIE_OFF,
101 CCI : CCI_OFF,
102 OUT : OUT_OFF,
103 COV : COV_OFF,
104 CCIFG : CCIFG_OFF
105 };
106
107 config Bits16 TACCR0 = 0; /*! Capture/Compare 0 */
108 config Bits16 TACCR1 = 0; /*! Capture/Compare 1 */
109 config Bits16 TACCR2 = 0; /*! Capture/Compare 2 */
110 config Bits16 TACCR3 = 0; /*! Capture/Compare 3 */
111 config Bits16 TACCR4 = 0; /*! Capture/Compare 4 */
112
113 /*! Timer interrupt enables */
114 config regIntVect_t interruptSource[6];
115
116 /*! Determine if each Register needs to be forced set or not */
117 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
118 [
119 { register : "TACTL" , regForceSet : false },
120 { register : "TACCTL0" , regForceSet : false },
121 { register : "TACCTL1" , regForceSet : false },
122 { register : "TACCTL2" , regForceSet : false },
123 { register : "TACCTL3" , regForceSet : false },
124 { register : "TACCTL4" , regForceSet : false },
125 { register : "TACCR0" , regForceSet : false },
126 { register : "TACCR1" , regForceSet : false },
127 { register : "TACCR2" , regForceSet : false },
128 { register : "TACCR3" , regForceSet : false },
129 { register : "TACCR4" , regForceSet : false }
130 ];
131 }