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12 /*!
13 * ======== Timer1_A2 ========
14 * MSP430 Timer1_A2 timer
15 */
16 metaonly module Timer1_A2 inherits ITimer_A {
17
18 instance:
19 /*! TA1CTL, Timer1_A2 Control Register */
20 config TACTL_t TA1CTL = {
21 TASSEL : TASSEL_0,
22 ID : ID_0,
23 MC : MC_0,
24 TACLR : TACLR_OFF,
25 TAIE : TAIE_OFF,
26 TAIFG : TAIFG_OFF
27 };
28
29 /*! TA1CCTL0, Capture/Compare Control Register 0 */
30 config TACCTLx_t TA1CCTL0 = {
31 CM : CM_0,
32 CCIS : CCIS_0,
33 SCS : SCS_OFF,
34 SCCI : SCCI_OFF,
35 CAP : CAP_OFF,
36 OUTMOD : OUTMOD_0,
37 CCIE : CCIE_OFF,
38 CCI : CCI_OFF,
39 OUT : OUT_OFF,
40 COV : COV_OFF,
41 CCIFG : CCIFG_OFF
42 };
43
44 /*! TA1CCTL1, Capture/Compare Control Register 1 */
45 config TACCTLx_t TA1CCTL1 = {
46 CM : CM_0,
47 CCIS : CCIS_0,
48 SCS : SCS_OFF,
49 SCCI : SCCI_OFF,
50 CAP : CAP_OFF,
51 OUTMOD : OUTMOD_0,
52 CCIE : CCIE_OFF,
53 CCI : CCI_OFF,
54 OUT : OUT_OFF,
55 COV : COV_OFF,
56 CCIFG : CCIFG_OFF
57 };
58
59 /*! TA1CCR0, Timer_A Capture/Compare Register 0 */
60 config Bits16 TA1CCR0 = 0;
61 /*! TA1CCR1, Timer_A Capture/Compare Register 1 */
62 config Bits16 TA1CCR1 = 0;
63
64 /*! Timer interrupt enables */
65 config regIntVect_t interruptSource[3];
66
67 /*! Determine if each Register needs to be forced set or not */
68 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
69 [
70 { register : "TA1CTL" , regForceSet : false },
71 { register : "TA1CCTL0" , regForceSet : false },
72 { register : "TA1CCTL1" , regForceSet : false },
73 { register : "TA1CCR0" , regForceSet : false },
74 { register : "TA1CCR1" , regForceSet : false }
75 ];
76 }