1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== Timer0_B7 ========
14 * MSP430 Timer0_B7 timer
15 */
16 metaonly module Timer0_B7 inherits ITimer_B {
17
18 /*! TB07IV Definitions */
19 enum IVValues {
20 TB0IV_NONE = 0x0000, /*! No Interrupt pending */
21 TB0IV_TBCCR1 = 0x0002, /*! TBCCR1_CCIFG */
22 TB0IV_TBCCR2 = 0x0004, /*! TBCCR2_CCIFG */
23 TB0IV_TBCCR3 = 0x0006, /*! TBCCR3_CCIFG */
24 TB0IV_TBCCR4 = 0x0008, /*! TBCCR4_CCIFG */
25 TB0IV_TBCCR5 = 0x000A, /*! TBCCR5_CCIFG */
26 TB0IV_TBCCR6 = 0x000C, /*! TBCCR6_CCIFG */
27 TB0IV_TBIFG = 0x000E /*! TBIFG */
28 };
29
30 instance:
31 /*! TB0CTL, Timer_B7 Control Register */
32 config TBCTL_t TB0CTL = {
33 TBCLGRP : TBCLGRP_0,
34 CNTL : CNTL_0,
35 TBSSEL : TBSSEL_0,
36 ID : ID_0,
37 MC : MC_0,
38 TBCLR : TBCLR_OFF,
39 TBIE : TBIE_OFF,
40 TBIFG : TBIFG_OFF
41 };
42
43 /*! TB0CCTL0, Capture/Compare Control Register 0 */
44 config TBCCTLx_t TB0CCTL0 = {
45 CM : CM_0,
46 CCIS : CCIS_0,
47 SCS : SCS_OFF,
48 CLLD : CLLD_0,
49 CAP : CAP_OFF,
50 OUTMOD : OUTMOD_0,
51 CCIE : CCIE_OFF,
52 CCI : CCI_OFF,
53 OUT : OUT_OFF,
54 COV : COV_OFF,
55 CCIFG : CCIFG_OFF
56 };
57
58 /*! TB0CCTL1, Capture/Compare Control Register 1 */
59 config TBCCTLx_t TB0CCTL1 = {
60 CM : CM_0,
61 CCIS : CCIS_0,
62 SCS : SCS_OFF,
63 CLLD : CLLD_0,
64 CAP : CAP_OFF,
65 OUTMOD : OUTMOD_0,
66 CCIE : CCIE_OFF,
67 CCI : CCI_OFF,
68 OUT : OUT_OFF,
69 COV : COV_OFF,
70 CCIFG : CCIFG_OFF
71 };
72
73 /*! TB0CCTL2, Capture/Compare Control Register 2 */
74 config TBCCTLx_t TB0CCTL2 = {
75 CM : CM_0,
76 CCIS : CCIS_0,
77 SCS : SCS_OFF,
78 CLLD : CLLD_0,
79 CAP : CAP_OFF,
80 OUTMOD : OUTMOD_0,
81 CCIE : CCIE_OFF,
82 CCI : CCI_OFF,
83 OUT : OUT_OFF,
84 COV : COV_OFF,
85 CCIFG : CCIFG_OFF
86 };
87
88 /*! TB0CCTL3, Capture/Compare Control Register 3 */
89 config TBCCTLx_t TB0CCTL3 = {
90 CM : CM_0,
91 CCIS : CCIS_0,
92 SCS : SCS_OFF,
93 CLLD : CLLD_0,
94 CAP : CAP_OFF,
95 OUTMOD : OUTMOD_0,
96 CCIE : CCIE_OFF,
97 CCI : CCI_OFF,
98 OUT : OUT_OFF,
99 COV : COV_OFF,
100 CCIFG : CCIFG_OFF
101 };
102
103 /*! TB0CCTL4, Capture/Compare Control Register 4 */
104 config TBCCTLx_t TB0CCTL4 = {
105 CM : CM_0,
106 CCIS : CCIS_0,
107 SCS : SCS_OFF,
108 CLLD : CLLD_0,
109 CAP : CAP_OFF,
110 OUTMOD : OUTMOD_0,
111 CCIE : CCIE_OFF,
112 CCI : CCI_OFF,
113 OUT : OUT_OFF,
114 COV : COV_OFF,
115 CCIFG : CCIFG_OFF
116 };
117
118 /*! TB0CCTL5, Capture/Compare Control Register 5 */
119 config TBCCTLx_t TB0CCTL5 = {
120 CM : CM_0,
121 CCIS : CCIS_0,
122 SCS : SCS_OFF,
123 CLLD : CLLD_0,
124 CAP : CAP_OFF,
125 OUTMOD : OUTMOD_0,
126 CCIE : CCIE_OFF,
127 CCI : CCI_OFF,
128 OUT : OUT_OFF,
129 COV : COV_OFF,
130 CCIFG : CCIFG_OFF
131 };
132
133 /*! TB0CCTL6, Capture/Compare Control Register 6 */
134 config TBCCTLx_t TB0CCTL6 = {
135 CM : CM_0,
136 CCIS : CCIS_0,
137 SCS : SCS_OFF,
138 CLLD : CLLD_0,
139 CAP : CAP_OFF,
140 OUTMOD : OUTMOD_0,
141 CCIE : CCIE_OFF,
142 CCI : CCI_OFF,
143 OUT : OUT_OFF,
144 COV : COV_OFF,
145 CCIFG : CCIFG_OFF
146 };
147
148 /*! TB0CCR0, Timer_B Capture/Compare Register 0 */
149 config Bits16 TB0CCR0 = 0;
150 /*! TB0CCR1, Timer_B Capture/Compare Register 1 */
151 config Bits16 TB0CCR1 = 0;
152 /*! TB0CCR2, Timer_B Capture/Compare Register 2 */
153 config Bits16 TB0CCR2 = 0;
154 /*! TB0CCR3, Timer_B Capture/Compare Register 3 */
155 config Bits16 TB0CCR3 = 0;
156 /*! TB0CCR4, Timer_B Capture/Compare Register 4 */
157 config Bits16 TB0CCR4 = 0;
158 /*! TB0CCR5, Timer_B Capture/Compare Register 5 */
159 config Bits16 TB0CCR5 = 0;
160 /*! TB0CCR6, Timer_B Capture/Compare Register 6 */
161 config Bits16 TB0CCR6 = 0;
162
163 /*! Timer interrupt enables */
164 config regIntVect_t interruptSource[8];
165
166 /*! Determine if each Register needs to be forced set or not */
167 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
168 [
169 { register : "TB0CTL" , regForceSet : false },
170 { register : "TB0CCTL0" , regForceSet : false },
171 { register : "TB0CCTL1" , regForceSet : false },
172 { register : "TB0CCTL2" , regForceSet : false },
173 { register : "TB0CCTL3" , regForceSet : false },
174 { register : "TB0CCTL4" , regForceSet : false },
175 { register : "TB0CCTL5" , regForceSet : false },
176 { register : "TB0CCTL6" , regForceSet : false },
177 { register : "TB0CCR0" , regForceSet : false },
178 { register : "TB0CCR1" , regForceSet : false },
179 { register : "TB0CCR2" , regForceSet : false },
180 { register : "TB0CCR3" , regForceSet : false },
181 { register : "TB0CCR4" , regForceSet : false },
182 { register : "TB0CCR5" , regForceSet : false },
183 { register : "TB0CCR6" , regForceSet : false }
184 ];
185 }