1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * Universal Serial Communication Interface
14 */
15 metaonly interface IUSCI_UART inherits IUSCI {
16
17
18
19
20
21 /*! Parity enable */
22 enum UCPEN_t {
23 UCPEN_OFF = 0x00, /*! Parity Disabled */
24 UCPEN = 0x02 /*! Parity Enabled */
25 };
26
27 /*! Parity select. UCPAR is not used when parity is disabled. */
28 enum UCPAR_t {
29 UCPAR_OFF = 0x00, /*! Odd parity */
30 UCPAR = 0x02 /*! Even parity */
31 };
32
33 /*! Stop bit select. Number of stop bits. */
34 enum UCSPB_t {
35 UCSPB_OFF = 0x00, /*! One stop bit */
36 UCSPB = 0x02 /*! Two stop bits */
37 };
38
39 /*! First modulation stage select */
40 enum UCBRF_t {
41 UCBRF_0 = 0x00, /*! First stage 0 */
42 UCBRF_1 = 0x10, /*! First stage 1 */
43 UCBRF_2 = 0x20, /*! First stage 2 */
44 UCBRF_3 = 0x30, /*! First stage 3 */
45 UCBRF_4 = 0x40, /*! First stage 4 */
46 UCBRF_5 = 0x50, /*! First stage 5 */
47 UCBRF_6 = 0x60, /*! First stage 6 */
48 UCBRF_7 = 0x70, /*! First stage 7 */
49 UCBRF_8 = 0x80, /*! First stage 8 */
50 UCBRF_9 = 0x90, /*! First stage 9 */
51 UCBRF_10 = 0xA0, /*! First stage 10 */
52 UCBRF_11 = 0xB0, /*! First stage 11 */
53 UCBRF_12 = 0xC0, /*! First stage 12 */
54 UCBRF_13 = 0xD0, /*! First stage 13 */
55 UCBRF_14 = 0xE0, /*! First stage 14 */
56 UCBRF_15 = 0xF0 /*! First stage 15 */
57 };
58
59 /*! Second modulation stage select */
60 enum UCBRS_t {
61 UCBRS_0 = 0x00, /*! Second stage 0 */
62 UCBRS_1 = 0x02, /*! Second stage 1 */
63 UCBRS_2 = 0x04, /*! Second stage 2 */
64 UCBRS_3 = 0x06, /*! Second stage 3 */
65 UCBRS_4 = 0x08, /*! Second stage 4 */
66 UCBRS_5 = 0x0A, /*! Second stage 5 */
67 UCBRS_6 = 0x0C, /*! Second stage 6 */
68 UCBRS_7 = 0x0E /*! Second stage 7 */
69 };
70
71 /*! Oversampling mode enabled */
72 enum UCOS16_t {
73 UCOS16_OFF = 0x00, /*! Disabled. */
74 UCOS16 = 0x02 /*! Enabled. */
75 };
76
77
78 /*! IRDA Transmit Pulse Length Bit 5 */
79 enum UCIRTXPL5_t {
80 UCIRTXPL5_OFF = 0x00, /*! Bit 5 OFF */
81 UCIRTXPL5 = 0x80 /*! Bit 5 ON */
82 };
83
84 /*! IRDA Transmit Pulse Length Bit 4 */
85 enum UCIRTXPL4_t {
86 UCIRTXPL4_OFF = 0x00, /*! Bit 4 OFF */
87 UCIRTXPL4 = 0x40 /*! Bit 4 ON */
88 };
89
90 /*! IRDA Transmit Pulse Length Bit 3 */
91 enum UCIRTXPL3_t {
92 UCIRTXPL3_OFF = 0x00, /*! Bit 3 OFF */
93 UCIRTXPL3 = 0x20 /*! Bit 3 ON */
94 };
95
96 /*! IRDA Transmit Pulse Length Bit 2 */
97 enum UCIRTXPL2_t {
98 UCIRTXPL2_OFF = 0x00, /*! Bit 2 OFF */
99 UCIRTXPL2 = 0x10 /*! Bit 2 ON */
100 };
101
102 /*! IRDA Transmit Pulse Length Bit 1 */
103 enum UCIRTXPL1_t {
104 UCIRTXPL1_OFF = 0x00, /*! Bit 1 OFF */
105 UCIRTXPL1 = 0x08 /*! Bit 1 ON */
106 };
107
108 /*! IRDA Transmit Pulse Length Bit 0 */
109 enum UCIRTXPL0_t {
110 UCIRTXPL0_OFF = 0x00, /*! Bit 0 OFF */
111 UCIRTXPL0 = 0x04 /*! Bit 0 ON */
112 };
113
114 /*! IrDA transmit pulse clock select. */
115 enum UCIRTXCLK_t {
116 UCIRTXCLK_OFF = 0x00, /*! BRCLK. */
117 UCIRTXCLK = 0x02 /*! BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. */
118 };
119
120 /*! IrDA encoder/decoder enable. */
121 enum UCIREN_t {
122 UCIREN_OFF = 0x00, /*! IrDA encoder/decoder disabled. */
123 UCIREN = 0x02 /*! IrDA encoder/decoder enabled. */
124 };
125
126 /*! IRDA Receive Filter Length Bit 5 */
127 enum UCIRRXFL5_t {
128 UCIRRXFL5_OFF = 0x00, /*! Bit 5 OFF */
129 UCIRRXFL5 = 0x80 /*! Bit 5 ON */
130 };
131
132 /*! IRDA Receive Filter Length Bit 4 */
133 enum UCIRRXFL4_t {
134 UCIRRXFL4_OFF = 0x00, /*! Bit 4 OFF */
135 UCIRRXFL4 = 0x40 /*! Bit 4 ON */
136 };
137
138 /*! IRDA Receive Filter Length Bit 3 */
139 enum UCIRRXFL3_t {
140 UCIRRXFL3_OFF = 0x00, /*! Bit 3 OFF */
141 UCIRRXFL3 = 0x20 /*! Bit 3 ON */
142 };
143
144 /*! IRDA Receive Filter Length Bit 2 */
145 enum UCIRRXFL2_t {
146 UCIRRXFL2_OFF = 0x00, /*! Bit 2 OFF */
147 UCIRRXFL2 = 0x10 /*! Bit 2 ON */
148 };
149
150 /*! IRDA Receive Filter Length Bit 1 */
151 enum UCIRRXFL1_t {
152 UCIRRXFL1_OFF = 0x00, /*! Bit 1 OFF */
153 UCIRRXFL1 = 0x08 /*! Bit 1 ON */
154 };
155
156 /*! IRDA Receive Filter Length Bit 0 */
157 enum UCIRRXFL0_t {
158 UCIRRXFL0_OFF = 0x00, /*! Bit 0 OFF */
159 UCIRRXFL0 = 0x04 /*! Bit 0 ON */
160 };
161
162 /*! IrDA receive input UCAxRXD polarity. */
163 enum UCIRRXPL_t {
164 UCIRRXPL_OFF = 0x00, /*! IrDA transceiver delivers a high pulse when a light pulse is seen. */
165 UCIRRXPL = 0x02 /*! IrDA transceiver delivers a low pulse when a light pulse is seen. */
166 };
167
168 /*! IrDA receive filter enabled. */
169 enum UCIRRXFE_t {
170 UCIRRXFE_OFF = 0x00, /*! Receive filter disabled. */
171 UCIRRXFE = 0x02 /*! Receive filter enabled. */
172 };
173
174 /*! Break/synch delimiter length bit 0 */
175 enum UCDELIM0_t {
176 UCDELIM0_OFF = 0x00, /*! Break Sync Delimiter bit 0 Off */
177 UCDELIM0 = 0x02 /*! Break Sync Delimiter bit 0 On */
178 };
179
180 /*! Break/synch delimiter length bit 1 */
181 enum UCDELIM1_t {
182 UCDELIM1_OFF = 0x00, /*! Break Sync Delimiter bit 1 Off */
183 UCDELIM1 = 0x02 /*! Break Sync Delimiter bit 1 On */
184 };
185
186 /*! Synch field time out error. */
187 enum UCSTOE_t {
188 UCSTOE_OFF = 0x00, /*! No error. */
189 UCSTOE = 0x02 /*! Length of synch field exceeded measurable time. */
190 };
191
192 /*! Break time out error. */
193 enum UCBTOE_t {
194 UCBTOE_OFF = 0x00, /*! No error. */
195 UCBTOE = 0x02 /*! Length of break field exceeded 22 bit times. */
196 };
197
198 /*! Automatic baud rate detect enable. */
199 enum UCABDEN_t {
200 UCABDEN_OFF = 0x00, /*! Baud rate detection disabled. Length of break and synch field is not
201 * measured. */
202 UCABDEN = 0x02 /*! Baud rate detection enabled. Length of break and synch field is
203 * measured and baud rate settings are changed accordingly. */
204 };
205
206 /*! USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. */
207 enum UCMODE_ASYNC_t {
208 UCMODE_0 = 0x00, /*! UART Mode. */
209 UCMODE_1 = 0x01, /*! Idle-Line Multiprocessor Mode. */
210 UCMODE_2 = 0x02, /*! Address-Bit Multiprocessor Mode. */
211 UCMODE_3 = 0x04 /*! UART Mode with automatic baud rate detection. */
212 };
213
214 /*! USCI clock source select. These bits select the BRCLK source clock. */
215 enum UCSSEL_UART_t {
216 UCSSEL_0 = 0x00, /*! UCLK */
217 UCSSEL_1 = 0x01, /*! ACLK */
218 UCSSEL_2 = 0x02 /*! SMCLK */
219
220 };
221
222 struct UCxCTL0_t {
223 UCPEN_t UCPEN; /*! Parity enable
224 * 0 Parity disabled.
225 * 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected
226 * (UCAxRXD). In address-bit multiprocessor mode, the address bit is
227 * included in the parity calculation. */
228 UCPAR_t UCPAR; /*! Parity select. UCPAR is not used when parity is disabled.
229 * 0 Odd parity
230 * 1 Even parity */
231 UCMSB_t UCMSB; /*! MSB first select. Controls the direction of the receive and transmit shift
232 *register.
233 * 0 LSB first
234 * 1 MSB first */
235 UC7BIT_t UC7BIT; /*! Character length. Selects 7-bit or 8-bit character length.
236 * 0 8-bit data
237 * 1 7-bit data */
238 UCSPB_t UCSPB; /*! Stop bit select. Number of stop bits.
239 * 0 One stop bit
240 * 1 Two stop bits */
241 UCMODE_ASYNC_t UCMODE; /*! USCI mode. The UCMODEx bits select the asynchronous mode when
242 *UCSYNC = 0.
243 * 00 UART Mode.
244 * 01 Idle-Line Multiprocessor Mode.
245 * 10 Address-Bit Multiprocessor Mode.
246 * 11 UART Mode with automatic baud rate detection. */
247 UCSYNC_t UCSYNC; /*!Synchronous mode enable
248 * 0 Asynchronous mode
249 * 1 Synchronous Mode */
250 }
251
252 struct UCxCTL1_t {
253 UCSSEL_UART_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
254 * 00 UCLK
255 * 01 ACLK
256 * 10 SMCLK
257 * 11 SMCLK */
258 UCRXEIE_t UCRXEIE; /*! Receive erroneous-character interrupt-enable
259 * 0 Erroneous characters rejected and UCAxRXIFG is not set
260 * 1 Erroneous characters received will set UCAxRXIFG */
261 UCBRKIE_t UCBRKIE; /*! Receive break character interrupt-enable
262 * 0 Received break characters do not set UCAxRXIFG.
263 * 1 Received break characters set UCAxRXIFG. */
264 UCDORM_t UCDORM; /*! Dormant. Puts USCI into sleep mode.
265 * 0 Not dormant. All received characters will set UCAxRXIFG.
266 * 1 Dormant. Only characters that are preceded by an idle-line or with
267 * address bit set will set UCAxRXIFG. In UART mode with automatic baud
268 * rate detection only the combination of a break and synch field will set
269 * UCAxRXIFG. */
270 UCTXADDR_t UCTXADDR; /*! Transmit address. Next frame to be transmitted will be marked as address
271 *depending on the selected multiprocessor mode.
272 * 0 Next frame transmitted is data
273 * 1 Next frame transmitted is an address */
274 UCTXBRK_t UCTXBRK; /*! Transmit break. Transmits a break with the next write to the transmit buffer.
275 *In UART mode with automatic baud rate detection 055h must be written
276 *into UCAxTXBUF to generate the required break/synch fields. Otherwise
277 *0h must be written into the transmit buffer.
278 * 0 Next frame transmitted is not a break
279 * 1 Next frame transmitted is a break or a break/synch */
280 UCSWRST_t UCSWRST; /*! Software reset enable
281 * 0 Disabled. USCI reset released for operation.
282 * 1 Enabled. USCI logic held in reset state. */
283 }
284
285 struct UCxMCTL_t {
286 UCBRF_t UCBRF; /*! First modulation stage select. These bits determine the modulation pattern
287 *for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. */
288 UCBRS_t UCBRS; /*! Second modulation stage select. These bits determine the modulation
289 *pattern for BITCLK. */
290 UCOS16_t UCOS16; /*! Oversampling mode enabled
291 * 0 Disabled
292 * 1 Enabled */
293 }
294
295 struct UCxSTAT_t {
296 UCLISTEN_t UCLISTEN; /*! Listen enable. The UCLISTEN bit selects loopback mode.
297 * 0 Disabled
298 * 1 Enabled. UCAxTXD is internally fed back to the receiver. */
299 UCFE_t UCFE; /*! Framing error flag
300 * 0 No error
301 * 1 Character received with low stop bit */
302 UCOE_t UCOE; /*! Overrun error flag. This bit is set when a character is transferred into
303 *UCAxRXBUF before the previous character was read. UCOE is cleared
304 *automatically when UCxRXBUF is read, and must not be cleared by
305 *software. Otherwise, it will not function correctly.
306 * 0 No error
307 * 1 Overrun error occurred */
308 UCPE_t UCPE; /*! Parity error flag. When UCPEN = 0, UCPE is read as 0.
309 * 0 No error
310 * 1 Character received with parity error */
311 UCBRK_t UCBRK; /*! Break detect flag
312 * 0 No break condition
313 * 1 Break condition occurred */
314 UCRXERR_t UCRXERR; /*! Receive error flag. This bit indicates a character was received with error(s).
315 *When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
316 *set. UCRXERR is cleared when UCAxRXBUF is read.
317 * 0 No receive errors detected
318 * 1 Receive error detected */
319 UCADDR_t UCADDR; /*! Address received in address-bit multiprocessor mode.
320 * 0 Received character is data
321 * 1 Received character is an address */
322 UCIDLE_t UCIDLE; /*! Idle line detected in idle-line multiprocessor mode.
323 * 0 No idle line detected
324 * 1 Idle line detected */
325 UCBUSY_t UCBUSY; /*! USCI busy. This bit indicates if a transmit or receive operation is in
326 *progress.
327 * 0 USCI inactive
328 * 1 USCI transmitting or receiving */
329 }
330
331 struct UCxIRTCTL_t {
332 UCIRTXPL5_t UCIRTXPL5; /*! IRDA Transmit Pulse Length Bit 5 */
333 UCIRTXPL4_t UCIRTXPL4; /*! IRDA Transmit Pulse Length Bit 4 */
334 UCIRTXPL3_t UCIRTXPL3; /*! IRDA Transmit Pulse Length Bit 3 */
335 UCIRTXPL2_t UCIRTXPL2; /*! IRDA Transmit Pulse Length Bit 2 */
336 UCIRTXPL1_t UCIRTXPL1; /*! IRDA Transmit Pulse Length Bit 1 */
337 UCIRTXPL0_t UCIRTXPL0; /*! IRDA Transmit Pulse Length Bit 0 */
338 UCIRTXCLK_t UCIRTXCLK; /*! IrDA transmit pulse clock select
339 * 0 BRCLK
340 * 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK */
341 UCIREN_t UCIREN; /*! IrDA encoder/decoder enable.
342 * 0 IrDA encoder/decoder disabled
343 * 1 IrDA encoder/decoder enabled */
344 }
345
346 struct UCxIRRCTL_t {
347 UCIRRXFL5_t UCIRRXFL5; /*! IRDA Receive Filter Length Bit 5 */
348 UCIRRXFL4_t UCIRRXFL4; /*! IRDA Receive Filter Length Bit 4 */
349 UCIRRXFL3_t UCIRRXFL3; /*! IRDA Receive Filter Length Bit 3 */
350 UCIRRXFL2_t UCIRRXFL2; /*! IRDA Receive Filter Length Bit 2 */
351 UCIRRXFL1_t UCIRRXFL1; /*! IRDA Receive Filter Length Bit 1 */
352 UCIRRXFL0_t UCIRRXFL0; /*! IRDA Receive Filter Length Bit 0 */
353 UCIRRXPL_t UCIRRXPL; /*! IrDA receive input UCAxRXD polarity
354 * 0 IrDA transceiver delivers a high pulse when a light pulse is seen
355 * 1 IrDA transceiver delivers a low pulse when a light pulse is seen */
356 UCIRRXFE_t UCIRRXFE; /*! IrDA receive filter enabled
357 * 0 Receive filter disabled
358 * 1 Receive filter enabled */
359 }
360
361 struct UCxABCTL_t {
362 UCDELIM1_t UCDELIM1; /*! Break/synch delimiter length
363 * 00 1 bit time
364 * 01 2 bit times
365 * 10 3 bit times
366 * 11 4 bit times */
367 UCDELIM0_t UCDELIM0; /*! Break/synch delimiter length
368 * 00 1 bit time
369 * 01 2 bit times
370 * 10 3 bit times
371 * 11 4 bit times */
372 UCSTOE_t UCSTOE; /*! Synch field time out error
373 * 0 No error
374 * 1 Length of synch field exceeded measurable time */
375 UCBTOE_t UCBTOE; /*! Break time out error
376 * 0 No error
377 * 1 Length of break field exceeded 22 bit times */
378 UCABDEN_t UCABDEN; /*! Automatic baud rate detect enable
379 * 0 Baud rate detection disabled. Length of break and synch field is not
380 * measured.
381 * 1 Baud rate detection enabled. Length of break and synch field is
382 * measured and baud rate settings are changed accordingly. */
383 }
384 }