1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== SD16_A ========
14 * MSP430F2xx Family SD16_A Module
15 */
16 metaonly module SD16_A inherits IADC {
17
18 /*! SD16XDIVx Bits */
19 enum SD16XDIV_t {
20 SD16XDIV_0 = 0x000, /*! Divide by 1 */
21 SD16XDIV_1 = 0x200, /*! Divide by 3 */
22 SD16XDIV_2 = 0x400, /*! Divide by 16 */
23 SD16XDIV_3 = 0x800 /*! Divide by 48 */
24 };
25
26 /*! SD16LP Bit */
27 enum SD16LP_t {
28 SD16LP_OFF = 0x000, /*! Low-power mode is disabled */
29 SD16LP = 0x100 /*! Low-power mode is enabled. The maximum clock frequency for the SD16_A is reduced */
30 };
31
32 /*! SD16DIVx Bits */
33 enum SD16DIV_t {
34 SD16DIV_0 = 0x00, /*! Divide by 1 */
35 SD16DIV_1 = 0x40, /*! Divide by 2 */
36 SD16DIV_2 = 0x80, /*! Divide by 4 */
37 SD16DIV_3 = 0xC0 /*! Divide by 8 */
38 };
39
40 /*! SD16SSELx Bits */
41 enum SD16SSEL_t {
42 SD16SSEL_0 = 0x00, /*! MCLK */
43 SD16SSEL_1 = 0x10, /*! SMCLK */
44 SD16SSEL_2 = 0x20, /*! ACLK */
45 SD16SSEL_3 = 0x30 /*! External TACLK */
46 };
47
48 /*! SD16VMIDON Bit */
49 enum SD16VMIDON_t {
50 SD16VMIDON_OFF = 0x00, /*! Off */
51 SD16VMIDON = 0x08 /*! On */
52 };
53
54 /*! SD16REFON Bit */
55 enum SD16REFON_t {
56 SD16REFON_OFF = 0x00, /*! Reference off */
57 SD16REFON = 0x04 /*! Reference on */
58 };
59
60 /*! SD16OVIE Bit */
61 enum SD16OVIE_t {
62 SD16OVIE_OFF = 0x00, /*! Overflow interrupt disabled */
63 SD16OVIE = 0x02 /*! Overflow interrupt enabled */
64 };
65
66 /*! SD16BUFx Bits */
67 enum SD16BUF_t {
68 SD16BUF_0 = 0x0000, /*! Buffer disabled */
69 SD16BUF_1 = 0x2000, /*! Slow speed/current */
70 SD16BUF_2 = 0x4000, /*! Medium speed/current */
71 SD16BUF_3 = 0x6000 /*! High speed/current */
72 };
73
74 /*! SD16UNI Bit */
75 enum SD16UNI_t {
76 SD16UNI_OFF = 0x0000, /*! Bipolar mode */
77 SD16UNI = 0x10000 /*! Unipolar mode */
78 };
79
80 /*! SD16XOSR Bit */
81 enum SD16XOSR_t {
82 SD16XOSR_OFF = 0x000, /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
83 * select the oversampling ratio. See SD16OSRx bit description for settings */
84 SD16XOSR = 0x800 /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
85 * select the oversampling ratio. See SD16OSRx bit description for settings */
86 };
87
88 /*! SD16SNGL Bit */
89 enum SD16SNGL_t {
90 SD16SNGL_OFF = 0x000, /*! Continuous conversion mode */
91 SD16SNGL = 0x400 /*! Single conversion mode */
92 };
93
94 /*! SD16OSRx Bits */
95 enum SD16OSR_t {
96 SD16OSR_256 = 0x000, /*! SD16XOSR = 0 */
97 SD16OSR_128 = 0x100, /*! SD16XOSR = 0 */
98 SD16OSR_64 = 0x200, /*! SD16XOSR = 0 */
99 SD16OSR_32 = 0x300, /*! SD16XOSR = 0 */
100 SD16OSR_512 = 0x800, /*! SD16XOSR = 1 */
101 SD16OSR_1024 = 0x900 /*! SD16XOSR = 1 */
102 };
103
104 /*! SD16LSBTOG Bit */
105 enum SD16LSBTOG_t {
106 SD16LSBTOG_OFF = 0x00, /*! SD16LSBACC does not toggle with each SD16MEM0 read */
107 SD16LSBTOG = 0x80 /*! SD16LSBACC toggles with each SD16MEM0 read */
108 };
109
110 /*! SD16LSBACC Bit */
111 enum SD16LSBACC_t {
112 SD16LSBACC_OFF = 0x00, /*! SD16MEMx contains the most significant 16-bits of the conversion */
113 SD16LSBACC = 0x40 /*! SD16MEMx contains the least significant 16-bits of the conversion */
114 };
115
116 /*! SD16OVIFG Bit */
117 enum SD16OVIFG_t {
118 SD16OVIFG_OFF = 0x00, /*! No overflow interrupt pending */
119 SD16OVIFG = 0x20 /*! Overflow interrupt pending */
120 };
121
122 /*! SD16DF Bit */
123 enum SD16DF_t {
124 SD16DF_OFF = 0x00, /*! Offset binary */
125 SD16DF = 0x10 /*! 2's complement */
126 };
127
128 /*! SD16IE Bit */
129 enum SD16IE_t {
130 SD16IE_OFF = 0x00, /*! Disabled */
131 SD16IE = 0x08 /*! Enabled */
132 };
133
134 /*! SD16IFG Bit */
135 enum SD16IFG_t {
136 SD16IFG_OFF = 0x00, /*! No interrupt pending */
137 SD16IFG = 0x04 /*! Interrupt pending */
138 };
139
140 /*! SD16SC Bit */
141 enum SD16SC_t {
142 SD16SC_OFF = 0x00, /*! No conversino start */
143 SD16SC = 0x02 /*! Start conversion */
144 };
145
146 /*! SD16INTDLYx Bits */
147 enum SD16INTDLY_t {
148 SD16INTDLY_0 = 0x00, /*! Fourth sample causes interrupt */
149 SD16INTDLY_1 = 0x40, /*! Third sample causes interrupt */
150 SD16INTDLY_2 = 0x80, /*! Second sample causes interrupt */
151 SD16INTDLY_3 = 0xC0 /*! First sample causes interrupt */
152 };
153
154 /*! SD16GAINx Bits */
155 enum SD16GAIN_t {
156 SD16GAIN_1 = 0x00, /*! Multiply by 1 */
157 SD16GAIN_2 = 0x08, /*! Multiply by 2 */
158 SD16GAIN_4 = 0x10, /*! Multiply by 4 */
159 SD16GAIN_8 = 0x18, /*! Multiply by 8 */
160 SD16GAIN_16 = 0x20, /*! Multiply by 16 */
161 SD16GAIN_32 = 0x28 /*! Multiply by 32 */
162 };
163
164 /*! SD16INCHx Bits */
165 enum SD16INCH_t {
166 SD16INCH_0 = 0x000, /*! A0 */
167 SD16INCH_1 = 0x001, /*! A1 */
168 SD16INCH_2 = 0x010, /*! A2 */
169 SD16INCH_3 = 0x011, /*! A3 */
170 SD16INCH_4 = 0x100, /*! A4 */
171 SD16INCH_5 = 0x101, /*! A5 - (AVcc - AVss)/11 */
172 SD16INCH_6 = 0x110, /*! A6 - Temperature Sensor */
173 SD16INCH_7 = 0x111 /*! A7 - Short PGA offset measurement */
174 };
175
176
177 /*! SD16_A Analog Enable Bit 7 */
178 enum SD16AE7_t {
179 SD16AE7_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
180 SD16AE7 = 0x0080 /*! External input enabled */
181 };
182
183 /*! SD16_A Analog Enable Bit 6 */
184 enum SD16AE6_t {
185 SD16AE6_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
186 SD16AE6 = 0x0040 /*! External input enabled */
187 };
188
189 /*! SD16_A Analog Enable Bit 5 */
190 enum SD16AE5_t {
191 SD16AE5_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
192 SD16AE5 = 0x0020 /*! External input enabled */
193 };
194
195 /*! SD16_A Analog Enable Bit 4 */
196 enum SD16AE4_t {
197 SD16AE4_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
198 SD16AE4 = 0x0010 /*! External input enabled */
199 };
200
201 /*! SD16_A Analog Enable Bit 3 */
202 enum SD16AE3_t {
203 SD16AE3_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
204 SD16AE3 = 0x0008 /*! External input enabled */
205 };
206
207 /*! SD16_A Analog Enable Bit 2 */
208 enum SD16AE2_t {
209 SD16AE2_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
210 SD16AE2 = 0x0004 /*! External input enabled */
211 };
212
213 /*! SD16_A Analog Enable Bit 1 */
214 enum SD16AE1_t {
215 SD16AE1_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
216 SD16AE1 = 0x0002 /*! External input enabled */
217 };
218
219 /*! SD16_A Analog Enable Bit 0 */
220 enum SD16AE0_t {
221 SD16AE0_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
222 SD16AE0 = 0x0001 /*! External input enabled */
223 };
224
225 /*! SD16_A Interrupt */
226 enum SD16IV_SD16OVIFG_t {
227 SD16IV_SD16OVIFG_OFF = 0x0000, /*! No Interrupt pending */
228 SD16IV_SD16OVIFG = 0x0002 /*! SD16OVIFG */
229 };
230
231 /*! SD16_A SD16MEMx overflow */
232 enum SD16IV_SD16MEM0_t {
233 SD16IV_SD16MEM0_OFF = 0x0000, /*! No Interrupt pending */
234 SD16IV_SD16MEM0 = 0x0004 /*! SD16MEM0 SD16IFG */
235 };
236
237 /*! SD16CTL Register */
238 struct SD16CTL_t {
239 SD16XDIV_t SD16XDIV; /*! SD16_A clock divider
240 * 000 Divide by 1
241 * 001 Divide by 3
242 * 010 Divide by 16
243 * 011 Divide by 48
244 * 1xx Reserved */
245 SD16LP_t SD16LP; /*! Low power mode. This bit selects a reduced speed, reduced power mode
246 * 0 Low-power mode is disabled
247 * 1 Low-power mode is enabled. The maximum clock frequency for the
248 * SD16_A is reduced. */
249 SD16DIV_t SD16DIV; /*! SD16_A clock divider
250 * 00 Divide by 1
251 * 01 Divide by 2
252 * 10 Divide by 4
253 * 11 Divide by 8 */
254 SD16SSEL_t SD16SSEL; /*! SD16_A clock source select
255 * 00 MCLK
256 * 01 SMCLK
257 * 10 ACLK
258 * External TACLK */
259 SD16VMIDON_t SD16VMIDON; /*! VMID buffer on
260 * 0 Off
261 * 1 On */
262 SD16REFON_t SD16REFON; /*! Reference generator on
263 * 0 Reference off
264 * 1 Reference on */
265 SD16OVIE_t SD16OVIE; /*! SD16_A overflow interrupt enable. The GIE bit must also be set to enable the
266 * interrupt.
267 * 0 Overflow interrupt disabled
268 * 1 Overflow interrupt enabled */
269 };
270
271 /*! SD16CCTL0 Register */
272 struct SD16CCTL0_t {
273 SD16UNI_t SD16UNI; /*! Unipolar mode select
274 * 0 Bipolar mode
275 * 1 Unipolar mode */
276 SD16XOSR_t SD16XOSR; /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
277 * select the oversampling ratio. See SD16OSRx bit description for settings. */
278 SD16SNGL_t SD16SNGL; /*! Single conversion mode select
279 * 0 Continuous conversion mode
280 * 1 Single conversion mode */
281 SD16OSR_t SD16OSR; /*! Oversampling ratio
282 * When SD16XOSR = 0
283 * 00 256
284 * 01 128
285 * 10 64
286 * 11 32
287 * When SD16XOSR = 1
288 * 00 512
289 * 01 1024
290 * 10 Reserved
291 * 11 Reserved */
292 SD16LSBTOG_t SD16LSBTOG; /*! LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time
293 * the SD16MEM0 register is read.
294 * 0 SD16LSBACC does not toggle with each SD16MEM0 read
295 * 1 SD16LSBACC toggles with each SD16MEM0 read */
296 SD16LSBACC_t SD16LSBACC; /*! LSB access. This bit allows access to the upper or lower 16-bits of the
297 * SD16_A conversion result.
298 * 0 SD16MEMx contains the most significant 16-bits of the conversion.
299 * 1 SD16MEMx contains the least significant 16-bits of the conversion. */
300 SD16OVIFG_t SD16OVIFG; /*! SD16_A overflow interrupt flag
301 * 0 No overflow interrupt pending
302 * 1 Overflow interrupt pending */
303 SD16DF_t SD16DF; /*! SD16_A data format
304 * 0 Offset binary
305 * 1 2's complement */
306 SD16IE_t SD16IE; /*! SD16_A interrupt enable
307 * 0 Disabled
308 * 1 Enabled */
309 SD16IFG_t SD16IFG; /*! SD16_A interrupt flag. SD16IFG is set when new conversion results are
310 * available. SD16IFG is automatically reset when the corresponding
311 * SD16MEMx register is read, or may be cleared with software.
312 * 0 No interrupt pending
313 * 1 Interrupt pending */
314 SD16SC_t SD16SC; /*! SD16_A start conversion
315 * 0 No conversion start
316 * 1 Start conversion */
317 };
318
319 /*! SD16INCTL0 Register */
320 struct SD16INCTL0_t {
321 SD16INTDLY_t SD16INTDLY; /*! Interrupt delay generation after conversion start. These bits select the
322 * delay for the first interrupt after conversion start.
323 * 00 Fourth sample causes interrupt
324 * 01 Third sample causes interrupt
325 * 10 Second sample causes interrupt
326 * 11 First sample causes interrupt */
327
328 SD16GAIN_t SD16GAIN; /*! SD16_A preamplifier gain
329 * 000 Multiply by 1
330 * 001 Multiply by 2
331 * 010 Multiply by 4
332 * 011 Multiply by 8
333 * 100 Multiply by 16
334 * 101 Multiply by 32
335 * 110 Reserved
336 * 111 Reserved */
337
338 SD16INCH_t SD16INCH; /*! SD16_A channel differential pair input
339 * 000 A0
340 * 001 A1
341 * 010 A2
342 * 011 A3
343 * 100 A4
344 * 101 A5-- (AVCC -- AVSS) / 11
345 * 110 A6 -- Temperature Sensor
346 * 111 A7 -- Short for PGA offset measurement */
347 };
348
349 /*! SD16_A Analog Input Enable Register */
350 struct SD16AE_t {
351 SD16AE0_t SD16AE0; /*! SD16_A analog enable
352 * 0 External input disabled. Negative inputs are internally connected to
353 * VSS.
354 * 1 External input enabled */
355 SD16AE1_t SD16AE1; /*! SD16_A analog enable
356 * 0 External input disabled. Negative inputs are internally connected to
357 * VSS.
358 * 1 External input enabled */
359 SD16AE2_t SD16AE2; /*! SD16_A analog enable
360 * 0 External input disabled. Negative inputs are internally connected to
361 * VSS.
362 * 1 External input enabled */
363 SD16AE3_t SD16AE3; /*! SD16_A analog enable
364 * 0 External input disabled. Negative inputs are internally connected to
365 * VSS.
366 * 1 External input enabled */
367 SD16AE4_t SD16AE4; /*! SD16_A analog enable
368 * 0 External input disabled. Negative inputs are internally connected to
369 * VSS.
370 * 1 External input enabled */
371 SD16AE5_t SD16AE5; /*! SD16_A analog enable
372 * 0 External input disabled. Negative inputs are internally connected to
373 * VSS.
374 * 1 External input enabled */
375 SD16AE6_t SD16AE6; /*! SD16_A analog enable
376 * 0 External input disabled. Negative inputs are internally connected to
377 * VSS.
378 * 1 External input enabled */
379 SD16AE7_t SD16AE7; /*! SD16_A analog enable
380 * 0 External input disabled. Negative inputs are internally connected to
381 * VSS.
382 * 1 External input enabled */
383 };
384
385 instance:
386
387 /*! SD16CTL Register */
388 config SD16CTL_t SD16CTL = {
389 SD16XDIV : SD16XDIV_0,
390 SD16LP : SD16LP_OFF,
391 SD16DIV : SD16DIV_0,
392 SD16SSEL : SD16SSEL_0,
393 SD16VMIDON : SD16VMIDON_OFF,
394 SD16REFON : SD16REFON_OFF,
395 SD16OVIE : SD16OVIE_OFF
396 };
397
398 /*! SD16CCTL0 Register */
399 config SD16CCTL0_t SD16CCTL0 = {
400 SD16UNI : SD16UNI_OFF,
401 SD16XOSR : SD16XOSR_OFF,
402 SD16SNGL : SD16SNGL_OFF,
403 SD16OSR : SD16OSR_256,
404 SD16LSBTOG : SD16LSBTOG_OFF,
405 SD16LSBACC : SD16LSBACC_OFF,
406 SD16OVIFG : SD16OVIFG_OFF,
407 SD16DF : SD16DF_OFF,
408 SD16IE : SD16IE_OFF,
409 SD16IFG : SD16IFG_OFF,
410 SD16SC : SD16SC_OFF
411 };
412
413 /*! SD16INCTL0 Register */
414 config SD16INCTL0_t SD16INCTL0 = {
415 SD16INTDLY : SD16INTDLY_0,
416 SD16GAIN : SD16GAIN_1,
417 SD16INCH : SD16INCH_0
418 };
419
420 /*! SD16AE Register */
421 config SD16AE_t SD16AE = {
422 SD16AE0 : SD16AE0_OFF,
423 SD16AE1 : SD16AE1_OFF,
424 SD16AE2 : SD16AE2_OFF,
425 SD16AE3 : SD16AE3_OFF,
426 SD16AE4 : SD16AE4_OFF,
427 SD16AE5 : SD16AE5_OFF,
428 SD16AE6 : SD16AE6_OFF,
429 SD16AE7 : SD16AE7_OFF
430 };
431
432 /*! SD16IV Register */
433 config Bits16 SD16IV = SD16IV_SD16OVIFG_OFF;
434
435 /*! SD16MEM0 Register */
436 config Bits16 SD16MEM0 = SD16IV_SD16MEM0_OFF;
437
438 /*! ADC10 has 1 interrupt enable */
439 config regIntVect_t interruptSource[2];
440
441 /*! Determine if each Register needs to be forced set or not */
442 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
443 [
444 { register : "SD16CTL" , regForceSet : false },
445 { register : "SD16CCTL0" , regForceSet : false },
446 { register : "SD16INCTL0" , regForceSet : false },
447 { register : "SD16AE" , regForceSet : false },
448 { register : "SD16IV" , regForceSet : false },
449 { register : "SD16MEM0" , regForceSet : false }
450 ];
451 }