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12 /*!
13 * ======== SFRIE1 ========
14 * MSP430 Interrupt Enable Register 1
15 */
16 metaonly module SFRIE1 inherits xdc.platform.IPeripheral {
17
18 enum JMBOUTIE_t {
19 JMBOUTIE_OFF = 0x00, /*! Interrupt not enabled */
20 JMBOUTIE = 0x80 /*! Interrupt enabled */
21 };
22
23 enum JMBINIE_t {
24 JMBINIE_OFF = 0x00, /*! Interrupt not enabled */
25 JMBINIE = 0x40 /*! Interrupt enabled */
26 };
27
28 enum ACCVIE_t {
29 ACCVIE_OFF = 0x00, /*! Interrupt not enabled */
30 ACCVIE = 0x20 /*! Interrupt enabled */
31 };
32
33 enum NMIIE_t {
34 NMIIE_OFF = 0x00, /*! Interrupt not enabled */
35 NMIIE = 0x10 /*! Interrupt enabled */
36 };
37
38 enum OFIE_t {
39 OFIE_OFF = 0x00, /*! Interrupt not enabled */
40 OFIE = 0x02 /*! Interrupt enabled */
41 };
42
43 enum WDTIE_t {
44 WDTIE_OFF = 0x00, /*! Interrupt not enabled */
45 WDTIE = 0x01 /*! Interrupt enabled */
46 };
47
48 enum NMIIFG_t {
49 NMIIFG_OFF = 0x00, /*! No interrupt pending */
50 NMIIFG = 0x10 /*! Interrupt pending */
51 };
52
53 enum WDTIFG_t {
54 WDTIFG_OFF = 0x00, /*! No interrupt pending */
55 WDTIFG = 0x01 /*! Interrupt pending */
56 };
57
58 enum OFIFG_t {
59 OFIFG_OFF = 0x00, /*! No interrupt pending */
60 OFIFG = 0x02 /*! Interrupt pending */
61 };
62
63 enum ACCVIFG_t {
64 ACCVIFG_OFF = 0x00, /*! No interrupt pending */
65 ACCVIFG = 0x20 /*! Interrupt pending */
66 };
67
68
69 struct IE1_t {
70 ACCVIE_t ACCVIE; /*! Flash memory access violation interrupt
71 * enable. This bit enables the ACCVIFG interrupt.
72 * 0 Interrupt disabled
73 * 1 Interrupt enabled */
74 NMIIE_t NMIIE; /*! NMI interrupt enable. This bit enables
75 *the NMI interrupt.
76 * 0 Interrupt disabled
77 * 1 Interrupt enabled */
78 OFIE_t OFIE; /*! Oscillator fault flag interrupt enable
79 *This bit enables the OFIFG interrupt.
80 * 0 Interrupt disabled
81 * 1 Interrupt enabled */
82 WDTIE_t WDTIE; /*! Watchdog timer+ interrupt enable. This
83 *bit enables the WDTIFG interrupt for
84 *interval timer mode. It is not necessary
85 *to set this bit for watchdog mode.
86 * 0 Interrupt disabled
87 * 1 Interrupt enabled */
88 }
89
90
91 struct IFG1_t {
92 ACCVIFG_t ACCVIFG; /*! Flash memory access violation interrupt
93 * flag.
94 * 0 No interrupt pending
95 * 1 Interrupt pending */
96 NMIIFG_t NMIIFG; /*! NMI interrupt flag.
97 * 0 No interrupt pending
98 * 1 Interrupt pending */
99 OFIFG_t OFIFG; /*! Oscillator fault interrupt flag
100 * 0 No interrupt pending
101 * 1 Interrupt pending */
102 WDTIFG_t WDTIFG; /*! Watchdog timer+ interrupt flag.
103 * 0 No interrupt pending
104 * 1 Interrupt pending */
105 }
106
107 /*!
108 * ======== ForceSetDefaultRegister_t ========
109 * Force Set Default Register
110 *
111 * Type to store if each register needs to be forced initialized
112 * even if the register is in default state.
113 *
114 * @see #ForceSetDefaultRegister_t
115 */
116 struct ForceSetDefaultRegister_t {
117 String register;
118 Bool regForceSet;
119 }
120
121 /*!
122 * ======== regIntVect_t ========
123 * Interrupt vector description
124 *
125 * Type to describe a single interrupt vector pin and all its possible
126 * configurations.
127 *
128 * @see #regIntVect_t
129 */
130 struct regIntVect_t {
131 String registerName;
132 String registerDescription;
133 String isrToggleString;
134 String priorityName;
135 Bool interruptEnable;
136 Bool interruptHandler;
137 Int priority;
138 }
139
140 instance:
141
142 /*! SFRIE1 interrupt enables
143 */
144 config regIntVect_t interruptSource[16];
145
146 /*! IE1, Interrupt Enable Register 1 */
147 config IE1_t SFRIE1 = {
148 ACCVIE : ACCVIE_OFF,
149 NMIIE : NMIIE_OFF,
150 OFIE : OFIE_OFF,
151 WDTIE : WDTIE_OFF
152 };
153
154 /*! IFG1, Interrupt Flag Register 1 */
155 config IFG1_t SFRIFG1 = {
156 ACCVIFG : ACCVIFG_OFF,
157 NMIIFG : NMIIFG_OFF,
158 OFIFG : OFIFG_OFF,
159 WDTIFG : WDTIFG_OFF
160 };
161
162 /*!
163 * ======== getSFRIE1 ========
164 * Gets a bit from the register in SFRIE1
165 *
166 * @see #getSFRIE1
167 */
168 Bool getSFRIE1(String register);
169
170 /*!
171 * ======== setSFRIE1 ========
172 * Sets a bit in the register SFRIE1
173 *
174 * @see #setSFRIE1
175 */
176 Bool setSFRIE1(String register, Bool set);
177
178 /*! Determine if each Register needs to be forced set or not */
179 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
180 [
181 { register : "SFRIE1" , regForceSet : false },
182 { register : "SFRIFG1" , regForceSet : false },
183 ];
184 }