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12 /*!
13 * ======== IE2 ========
14 * MSP430 Interrupt Enable Register 2
15 */
16 metaonly module IE2 inherits xdc.platform.IPeripheral {
17
18
19 enum UCB0TXIE_t {
20 UCB0TXIE_OFF = 0x00, /*! Interrupt disabled */
21 UCB0TXIE = 0x08 /*! Interrupt enabled */
22 };
23
24
25 enum UCB0RXIE_t {
26 UCB0RXIE_OFF = 0x00, /*! Interrupt disabled */
27 UCB0RXIE = 0x04 /*! Interrupt enabled */
28 };
29
30
31 enum UCA0TXIE_t {
32 UCA0TXIE_OFF = 0x00, /*! Interrupt disabled */
33 UCA0TXIE = 0x02 /*! Interrupt enabled */
34 };
35
36
37 enum UCA0RXIE_t {
38 UCA0RXIE_OFF = 0x00, /*! Interrupt disabled */
39 UCA0RXIE = 0x01 /*! Interrupt enabled */
40 };
41
42
43 enum UCB0TXIFG_t {
44 UCB0TXIFG_OFF = 0x00, /*! No interrupt pending */
45 UCB0TXIFG = 0x08 /*! Interrupt pending */
46 };
47
48
49 enum UCB0RXIFG_t {
50 UCB0RXIFG_OFF = 0x00, /*! No interrupt pending */
51 UCB0RXIFG = 0x04 /*! Interrupt pending */
52 };
53
54
55 enum UCA0TXIFG_t {
56 UCA0TXIFG_OFF = 0x00, /*! No interrupt pending */
57 UCA0TXIFG = 0x02 /*! Interrupt pending */
58 };
59
60
61 enum UCA0RXIFG_t {
62 UCA0RXIFG_OFF = 0x00, /*! No interrupt pending */
63 UCA0RXIFG = 0x01 /*! Interrupt pending */
64 };
65
66 /*! IE2, Interrupt Enable Register 2 */
67 struct IE2_t {
68 UCB0TXIE_t UCB0TXIE; /*! USCI_B0 transmit interrupt enable
69 * 0 Interrupt disabled
70 * 1 Interrupt enabled */
71 UCB0RXIE_t UCB0RXIE; /*! USCI_B0 receive interrupt enable
72 * 0 Interrupt disabled
73 * 1 Interrupt enabled */
74 UCA0TXIE_t UCA0TXIE; /*! USCI_A0 transmit interrupt enable
75 * 0 Interrupt disabled
76 * 1 Interrupt enabled */
77 UCA0RXIE_t UCA0RXIE; /*! USCI_A0 receive interrupt enable
78 * 0 Interrupt disabled
79 * 1 Interrupt enabled */
80 }
81
82 /*! IFG2, Interrupt Flag Register 2 */
83 struct IFG2_t {
84 UCB0TXIFG_t UCB0TXIFG; /*! USCI_B0 transmit interrupt flag
85 * 0 No interrupt pending
86 * 1 Interrupt pending */
87 UCB0RXIFG_t UCB0RXIFG; /*! USCI_B0 receive interrupt flag
88 * 0 No interrupt pending
89 * 1 Interrupt pending */
90 UCA0TXIFG_t UCA0TXIFG; /*! USCI_A0 transmit interrupt flag
91 * 0 No interrupt pending
92 * 1 Interrupt pending */
93 UCA0RXIFG_t UCA0RXIFG; /*! USCI_A0 receive interrupt flag
94 * 0 No interrupt pending
95 * 1 Interrupt pending */
96 }
97
98 /*!
99 * ======== regIntVect_t ========
100 * Interrupt vector description
101 *
102 * Type to describe a single interrupt vector pin and all its possible
103 * configurations.
104 *
105 * @see #regIntVect_t
106 */
107 struct regIntVect_t {
108 String registerName;
109 String registerDescription;
110 String isrToggleString;
111 String priorityName;
112 Bool interruptEnable;
113 Bool interruptHandler;
114 Int priority;
115 }
116
117 /*!
118 * ======== ForceSetDefaultRegister_t ========
119 * Force Set Default Register
120 *
121 * Type to store if each register needs to be forced initialized
122 * even if the register is in default state.
123 *
124 * @see #ForceSetDefaultRegister_t
125 */
126 struct ForceSetDefaultRegister_t {
127 String register;
128 Bool regForceSet;
129 }
130
131 instance:
132 /*! IE2, Interrupt Enable Register 2 */
133 config IE2_t IE2 = {
134 UCB0TXIE : UCB0TXIE_OFF,
135 UCB0RXIE : UCB0RXIE_OFF,
136 UCA0TXIE : UCA0TXIE_OFF,
137 UCA0RXIE : UCA0RXIE_OFF,
138 };
139
140 /*! IFG2, Interrupt Flag Register 2 */
141 config IFG2_t IFG2 = {
142 UCB0TXIFG : UCB0TXIFG_OFF,
143 UCB0RXIFG : UCB0RXIFG_OFF,
144 UCA0TXIFG : UCA0TXIFG_OFF,
145 UCA0RXIFG : UCA0RXIFG_OFF,
146 };
147
148 /*!
149 * ======== getUCB0TXIE ========
150 * Gets UCB0TXIE bit
151 *
152 * @see #getUCB0TXIE
153 */
154 Bool getUCB0TXIE();
155
156 /*!
157 * ======== setUCB0TXIE ========
158 * Sets UCB0TXIE bit
159 *
160 * @see #setUCB0TXIE
161 */
162 Bool setUCB0TXIE(Bool set);
163
164 /*!
165 * ======== getUCB0RXIE ========
166 * Gets UCB0RXIE bit
167 *
168 * @see #getUCB0RXIE
169 */
170 Bool getUCB0RXIE();
171
172 /*!
173 * ======== setUCB0RXIE ========
174 * Sets UCB0RXIE bit
175 *
176 * @see #setUCB0RXIE
177 */
178 Bool setUCB0RXIE(Bool set);
179
180 /*!
181 * ======== getUCA0TXIE ========
182 * Gets UCA0TXIE bit
183 *
184 * @see #getUCA0TXIE
185 */
186 Bool getUCA0TXIE();
187
188 /*!
189 * ======== setUCA0TXIE ========
190 * Sets UCA0TXIE bit
191 *
192 * @see #setUCA0TXIE
193 */
194 Bool setUCA0TXIE(Bool set);
195
196 /*!
197 * ======== getUCA0RXIE ========
198 * Gets UCA0RXIE bit
199 *
200 * @see #getUCA0RXIE
201 */
202 Bool getUCA0RXIE();
203
204 /*!
205 * ======== setUCA0RXIE ========
206 * Sets UCA0RXIE bit
207 *
208 * @see #setUCA0RXIE
209 */
210 Bool setUCA0RXIE(Bool set);
211
212 /*! IE2 interrupt enables
213 */
214 config regIntVect_t interruptSource[8];
215
216 /*!
217 * ======== forceSetDefaultRegister ========
218 * Determine if each Register needs to be forced set or not
219 */
220 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
221 [
222 { register : "IE2" , regForceSet : false },
223 { register : "IFG2" , regForceSet : false },
224 ];
225 }