1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Universal Serial Communication Interface
16 */
17 metaonly module USCI_A1_UART_2xx inherits IUSCI_A1_UART {
18
19
20 21 22
23 create(IClock.Instance clock);
24
25 /*! USCI_A1 transmit interrupt enable */
26 enum UCA1TXIE_t {
27 UCA1TXIE_OFF = 0x00, /*! Interrupt disabled */
28 UCA1TXIE = 0x02 /*! Interrupt enabled */
29 };
30
31 /*! USCI_A1 receive interrupt enable */
32 enum UCA1RXIE_t {
33 UCA1RXIE_OFF = 0x00, /*! Interrupt disabled */
34 UCA1RXIE = 0x01 /*! Interrupt enabled */
35 };
36
37 /*! USCI_Ax UART Interrupt Enable Register */
38 struct UC1IE_t {
39 UCA1TXIE_t UCA1TXIE; /*! USCI_A1 transmit interrupt enable
40 * 0 Interrupt disabled
41 * 1 Interrupt enabled */
42 UCA1RXIE_t UCA1RXIE; /*! USCI_A1 receive interrupt enable
43 * 0 Interrupt disabled
44 * 1 Interrupt enabled */
45 }
46
47 instance:
48 /*! @_nodoc */
49 config IClock.Instance clock;
50
51 /*! USCI_A1 Interrupt Enable Register */
52 config UC1IE_t UC1IE = {
53 UCA1TXIE : UCA1TXIE_OFF,
54 UCA1RXIE : UCA1RXIE_OFF
55 };
56
57 /*! USCI_A1 UART interrupt enables */
58 config regIntVect_t interruptSource[2];
59
60 /*! Determine if each Register needs to be forced set or not */
61 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
62 [
63 { register : "UCA1CTL0" , regForceSet : false },
64 { register : "UCA1CTL1" , regForceSet : false },
65 { register : "UCA1BR0" , regForceSet : false },
66 { register : "UCA1BR1" , regForceSet : false },
67 { register : "UCA1MCTL" , regForceSet : false },
68 { register : "UCA1STAT" , regForceSet : false },
69 { register : "UCA1RXBUF" , regForceSet : false },
70 { register : "UCA1TXBUF" , regForceSet : false },
71 { register : "UCA1ABCTL" , regForceSet : false },
72 { register : "UCA1IRTCTL" , regForceSet : false },
73 { register : "UCA1IRRCTL" , regForceSet : false },
74 { register : "UC1IE" , regForceSet : false }
75 ];
76 }