1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== IE1 ========
14 * MSP430 Interrupt Enable Register 1
15 */
16 metaonly module IE1 inherits xdc.platform.IPeripheral {
17
18 enum NMIIE_t {
19 NMIIE_OFF = 0x00, /*! Interrupt not enabled */
20 NMIIE = 0x10 /*! Interrupt enabled */
21 };
22
23 enum WDTIE_t {
24 WDTIE_OFF = 0x00, /*! Interrupt not enabled */
25 WDTIE = 0x01 /*! Interrupt enabled */
26 };
27
28 enum OFIE_t {
29 OFIE_OFF = 0x00, /*! Interrupt not enabled */
30 OFIE = 0x02 /*! Interrupt enabled */
31 };
32
33 enum ACCVIE_t {
34 ACCVIE_OFF = 0x00, /*! Interrupt not enabled */
35 ACCVIE = 0x20 /*! Interrupt enabled */
36 };
37
38 enum NMIIFG_t {
39 NMIIFG_OFF = 0x00, /*! No interrupt pending */
40 NMIIFG = 0x10 /*! Interrupt pending */
41 };
42
43 enum WDTIFG_t {
44 WDTIFG_OFF = 0x00, /*! No interrupt pending */
45 WDTIFG = 0x01 /*! Interrupt pending */
46 };
47
48 enum OFIFG_t {
49 OFIFG_OFF = 0x00, /*! No interrupt pending */
50 OFIFG = 0x02 /*! Interrupt pending */
51 };
52
53 enum ACCVIFG_t {
54 ACCVIFG_OFF = 0x00, /*! No interrupt pending */
55 ACCVIFG = 0x20 /*! Interrupt pending */
56 };
57
58
59 struct IE1_t {
60 ACCVIE_t ACCVIE; /*! Flash memory access violation interrupt
61 * enable. This bit enables the ACCVIFG interrupt.
62 * 0 Interrupt disabled
63 * 1 Interrupt enabled */
64 NMIIE_t NMIIE; /*! NMI interrupt enable. This bit enables
65 *the NMI interrupt.
66 * 0 Interrupt disabled
67 * 1 Interrupt enabled */
68 OFIE_t OFIE; /*! Oscillator fault flag interrupt enable
69 *This bit enables the OFIFG interrupt.
70 * 0 Interrupt disabled
71 * 1 Interrupt enabled */
72 WDTIE_t WDTIE; /*! Watchdog timer+ interrupt enable. This
73 *bit enables the WDTIFG interrupt for
74 *interval timer mode. It is not necessary
75 *to set this bit for watchdog mode.
76 * 0 Interrupt disabled
77 * 1 Interrupt enabled */
78 }
79
80
81 struct IFG1_t {
82 ACCVIFG_t ACCVIFG; /*! Flash memory access violation interrupt
83 * flag.
84 * 0 No interrupt pending
85 * 1 Interrupt pending */
86 NMIIFG_t NMIIFG; /*! NMI interrupt flag.
87 * 0 No interrupt pending
88 * 1 Interrupt pending */
89 OFIFG_t OFIFG; /*! Oscillator fault interrupt flag
90 * 0 No interrupt pending
91 * 1 Interrupt pending */
92 WDTIFG_t WDTIFG; /*! Watchdog timer+ interrupt flag.
93 * 0 No interrupt pending
94 * 1 Interrupt pending */
95 }
96
97 /*!
98 * ======== ForceSetDefaultRegister_t ========
99 * Force Set Default Register
100 *
101 * Type to store if each register needs to be forced initialized
102 * even if the register is in default state.
103 *
104 * @see #ForceSetDefaultRegister_t
105 */
106 struct ForceSetDefaultRegister_t {
107 String register;
108 Bool regForceSet;
109 }
110
111 instance:
112 /*! IE1, Interrupt Enable Register 1 */
113 config IE1_t IE1 = {
114 ACCVIE : ACCVIE_OFF,
115 NMIIE : NMIIE_OFF,
116 OFIE : OFIE_OFF,
117 WDTIE : WDTIE_OFF
118 };
119
120 /*! IFG1, Interrupt Flag Register 1 */
121 config IFG1_t IFG1 = {
122 ACCVIFG : ACCVIFG_OFF,
123 NMIIFG : NMIIFG_OFF,
124 OFIFG : OFIFG_OFF,
125 WDTIFG : WDTIFG_OFF
126 };
127
128 /*!
129 * ======== getWDTIE ========
130 * Gets WDTIE bit
131 *
132 * @see #getWDTIE
133 */
134 Bool getWDTIE();
135
136 /*!
137 * ======== setWDTIE ========
138 * Sets WDTIE bit
139 *
140 * @see #setWDTIE
141 */
142 Bool setWDTIE(Bool set);
143
144 /*!
145 * ======== getWDTIFG ========
146 * Gets WDTIFG bit
147 *
148 * @see #getWDTIFG
149 */
150 Bool getWDTIFG();
151
152 /*!
153 * ======== setWDTIFG ========
154 * Sets WDTIFG bit
155 *
156 * @see #setWDTIFG
157 */
158 Bool setWDTIFG(Bool set);
159
160 /*!
161 * ======== getOFIE ========
162 * Gets OFIE bit
163 *
164 * @see #getOFIE
165 */
166 Bool getOFIE();
167
168 /*!
169 * ======== setOFIE ========
170 * Sets OFIE bit
171 *
172 * @see #setOFIE
173 */
174 Bool setOFIE(Bool set);
175
176 /*!
177 * ======== getOFIFG ========
178 * Gets OFIFG bit
179 *
180 * @see #getOFIFG
181 */
182 Bool getOFIFG();
183
184 /*!
185 * ======== setOFIFG ========
186 * Sets OFIFG bit
187 *
188 * @see #setOFIFG
189 */
190 Bool setOFIFG(Bool set);
191
192 /*!
193 * ======== getNMIIE ========
194 * Gets NMIIE bit
195 *
196 * @see #getNMIIE
197 */
198 Bool getNMIIE();
199
200 /*!
201 * ======== setNMIIE ========
202 * Sets NMIIE bit
203 *
204 * @see #setNMIIE
205 */
206 Bool setNMIIE(Bool set);
207
208 /*!
209 * ======== getNMIIFG ========
210 * Gets NMIIFG bit
211 *
212 * @see #getNMIIFG
213 */
214 Bool getNMIIFG();
215
216 /*!
217 * ======== setNMIIFG ========
218 * Sets NMIIFG bit
219 *
220 * @see #setNMIIFG
221 */
222 Bool setNMIIFG(Bool set);
223
224 /*!
225 * ======== getACCVIE ========
226 * Gets ACCVIE bit
227 *
228 * @see #getACCVIE
229 */
230 Bool getACCVIE();
231
232 /*!
233 * ======== setACCVIE ========
234 * Sets ACCVIE bit
235 *
236 * @see #setACCVIE
237 */
238 Bool setACCVIE(Bool set);
239
240 /*!
241 * ======== getACCVIFG ========
242 * Gets ACCVIFG bit
243 *
244 * @see #getACCVIFG
245 */
246 Bool getACCVIFG();
247
248 /*!
249 * ======== setACCVIFG ========
250 * Sets ACCVIFG bit
251 *
252 * @see #setACCVIFG
253 */
254 Bool setACCVIFG(Bool set);
255
256 /*! Determine if each Register needs to be forced set or not */
257 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
258 [
259 { register : "IE1" , regForceSet : false },
260 { register : "IFG1" , regForceSet : false },
261 ];
262 }