1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Universal Serial Communication Interface B0 SPI 2xx
16 */
17 metaonly module USCI_B0_SPI_2xx inherits IUSCI_B0_SPI {
18
19 20 21
22 create(IClock.Instance clock);
23
24 instance:
25 /*! @_nodoc */
26 config IClock.Instance clock;
27
28 /*! Determine if each Register needs to be forced set or not */
29 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
30 [
31 { register : "UCB0CTL0" , regForceSet : false },
32 { register : "UCB0CTL1" , regForceSet : false },
33 { register : "UCB0BR0" , regForceSet : false },
34 { register : "UCB0BR1" , regForceSet : false },
35 { register : "UCB0STAT" , regForceSet : false },
36 { register : "UCB0RXBUF" , regForceSet : false },
37 { register : "UCB0TXBUF" , regForceSet : false }
38 ];
39 }