1 /*
2 * Copyright (c) 2012 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Platform.xdc ========
15 * Platform support for evmC6A8149
16 *
17 */
18
19 package ti.platforms.evmC6A8149;
20
21 /*!
22 * ======== Platform ========
23 * Platform support for the evmC6A8149
24 *
25 * This module implements xdc.platform.IPlatform and defines configuration
26 * parameters that correspond to this platform's Cpu's, Board's, etc.
27 *
28 * The configuration parameters are initialized in this package's
29 * configuration script (package.cfg) and "bound" to the TCOM object
30 * model. Once they are part of the model, these parameters are
31 * queried by a program's configuration script.
32 *
33 * This particular platform has 4 CPU's, a host GPP, 2 M3's, and a
34 * C674 DSP.
35 */
36 metaonly module Platform inherits xdc.platform.IPlatform
37 {
38 readonly config xdc.platform.IPlatform.Board BOARD = {
39 id: "0",
40 boardName: "evmC6A8149",
41 boardFamily: "evmC6A8149",
42 boardRevision: null
43 };
44
45 /* C674 GEM */
46 readonly config xdc.platform.IExeContext.Cpu GEM = {
47 id: "0",
48 clockRate: 500.0,
49 catalogName: "ti.catalog.c6000",
50 deviceName: "TMS320C6A8149",
51 revision: ""
52 };
53
54
55 /* EVE - ARP32 */
56 readonly config xdc.platform.IExeContext.Cpu EVE = {
57 id: "1",
58 clockRate: 225.0,
59 catalogName: "ti.catalog.arp32",
60 deviceName: "TMS320C6A8149",
61 revision: ""
62 };
63
64 /* M3 Subsystem */
65 readonly config xdc.platform.IExeContext.Cpu DSS = {
66 id: "2",
67 clockRate: 200.0,
68 catalogName: "ti.catalog.arm.cortexm3",
69 deviceName: "TMS320C6A8149",
70 revision: "1.0"
71 };
72
73 /* GPP */
74 readonly config xdc.platform.IExeContext.Cpu GPP = {
75 id: "3",
76 clockRate: 600.0, /* Typically set by the HLOS */
77 catalogName: "ti.catalog.arm.cortexa8",
78 deviceName: "TMS320C6A8149",
79 revision: "1.0"
80 };
81
82 instance:
83
84 override readonly config xdc.platform.IPlatform.Memory
85 externalMemoryMap[string] = [
86 ["DDR3_HOST", {
87 comment: "DDR3 Memory reserved for use by the A8",
88 name: "DDR3_HOST",
89 base: 0x80000000,
90 len: 0x0B000000 /* 176 MB */
91 }],
92 ["DDR3_DSP", {
93 comment: "DDR3 Memory reserved for use by the C674",
94 name: "DDR3_DSP",
95 base: 0x8B000000,
96 len: 0x02000000 /* 32 MB */
97 }],
98 ["DDR3_SR1", {
99 comment: "DDR3 Memory reserved for use by SharedRegion 1",
100 name: "DDR3_SR1",
101 base: 0x8D000000,
102 len: 0x00C00000 /* 12 MB */
103 }],
104 ["DDR3_HDVPSS", {
105 comment: "DDR3 Memory reserved for use by HDVPSS",
106 name: "DDR3_HDVPSS",
107 base: 0x8DC00000,
108 len: 0x00200000 /* 2 MB */
109 }],
110 ["DDR3_V4L2", {
111 comment: "DDR3 Memory reserved for use by V4L2",
112 name: "DDR3_V4L2",
113 base: 0x8DE00000,
114 len: 0x00200000 /* 2 MB */
115 }],
116 ["DDR3_SR0", {
117 comment: "DDR3 Memory reserved for use by SharedRegion 0",
118 name: "DDR3_SR0",
119 base: 0x8E000000,
120 len: 0x01000000 /* 16 MB */
121 }],
122 ["DDR3_M3", {
123 comment: "DDR3 Memory reserved for use by the M3 core",
124 name: "DDR3_M3",
125 base: 0x8F000000,
126 len: 0x01000000 /* 16 MB */
127 }],
128 ["DDR3_EVEVECS", {
129 comment: "DDR3 Memory reserved for use by the EVE int vectors",
130 name: "DDR3_EVEVECS",
131 base: 0x90000000,
132 len: 0x00000100 /* 256 Bytes */
133 }],
134 ["DDR3_EVE", {
135 comment: "DDR3 Memory reserved for use by the EVE",
136 name: "DDR3_EVE",
137 base: 0x90000100,
138 len: 0x00FFFF00 /* 16MB - 256 Bytes */
139 }],
140 ];
141
142 /*
143 * ======== l1PMode ========
144 * Define the amount of L1P RAM used for L1 Program Cache.
145 *
146 * Check the device documentation for valid values.
147 */
148 config String l1PMode = "32k";
149
150 /*
151 * ======== l1DMode ========
152 * Define the amount of L1D RAM used for L1 Data Cache.
153 *
154 * Check the device documentation for valid values.
155 */
156 config String l1DMode = "32k";
157
158 /*
159 * ======== l2Mode ========
160 * Define the amount of L2 RAM used for L2 Cache.
161 *
162 * Check the device documentation for valid values.
163 */
164 config String l2Mode = "0k";
165 };
166 /*
167 * @(#) ti.platforms.evmC6A8149; 1, 0, 0,6; 7-3-2012 15:23:40; /db/ztree/library/trees/platform/platform-n23x/src/
168 */
169