1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.communication.USI as USI;
13 import ti.catalog.msp430.peripherals.adc.ADC10 as ADC10;
14
15 /*!
16 * ======== GPIO for MSP430G2x32 ========
17 * MSP430 General Purpose Input Output Ports
18 */
19 metaonly module GPIO_MSP430G2x32 inherits IGPIO {
20 /*!
21 * ======== create ========
22 * Create an instance of this peripheral.
23 */
24 create(USI.Instance usi, ADC10.Instance adc10);
25
26 instance:
27 /*! @_nodoc */
28 config USI.Instance usi;
29
30 /*! @_nodoc */
31 config ADC10.Instance adc10;
32
33 /*! Define an array to describe all device pins. The 1st dimension
34 * denotes the port, the second the pin on that port. On an
35 * MSP430G2x32 device, there are 8 + 8 = 16 pins total.
36 */
37
38 39
40 41
42 config DevicePin_t devicePins[2][8];
43
44 /*! Implementation of Device Pin Functional Configuration */
45 override config DevicePinFunctionSetting_t devicePinSetting[2][8];
46
47 /*! Determine if each Register needs to be forced set or not */
48 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
49 [
50 { register : "P1OUT" , regForceSet : true },
51 { register : "P1SEL" , regForceSet : false },
52 { register : "P1SEL2", regForceSet : false },
53 { register : "P1DIR" , regForceSet : false },
54 { register : "P1REN" , regForceSet : false },
55 { register : "P1IES" , regForceSet : true },
56 { register : "P1IFG" , regForceSet : true },
57 { register : "P1IE" , regForceSet : false },
58 { register : "P2OUT" , regForceSet : true },
59 { register : "P2SEL" , regForceSet : false },
60 { register : "P2SEL2", regForceSet : false },
61 { register : "P2DIR" , regForceSet : false },
62 { register : "P2REN" , regForceSet : false },
63 { register : "P2IES" , regForceSet : true },
64 { register : "P2IFG" , regForceSet : true },
65 { register : "P2IE" , regForceSet : false }
66 ];
67
68 69 70 71 72 73
74
75 /*! Port 1 Output Register */
76 config GpioBits8PxOut_t P1OUT = {
77 Bit0 : BIT0_OFF,
78 Bit1 : BIT1_OFF,
79 Bit2 : BIT2_OFF,
80 Bit3 : BIT3_OFF,
81 Bit4 : BIT4_OFF,
82 Bit5 : BIT5_OFF,
83 Bit6 : BIT6_OFF,
84 Bit7 : BIT7_OFF
85 };
86
87 /*! Port 1 Port Select Register */
88 config GpioBits8PxSel_t P1SEL = {
89 Bit0 : BIT0_OFF,
90 Bit1 : BIT1_OFF,
91 Bit2 : BIT2_OFF,
92 Bit3 : BIT3_OFF,
93 Bit4 : BIT4_OFF,
94 Bit5 : BIT5_OFF,
95 Bit6 : BIT6_OFF,
96 Bit7 : BIT7_OFF
97 };
98
99 /*! Port 1 Port Select 2 Register */
100 config GpioBits8PxSel2_t P1SEL2 = {
101 Bit0 : BIT0_OFF,
102 Bit1 : BIT1_OFF,
103 Bit2 : BIT2_OFF,
104 Bit3 : BIT3_OFF,
105 Bit4 : BIT4_OFF,
106 Bit5 : BIT5_OFF,
107 Bit6 : BIT6_OFF,
108 Bit7 : BIT7_OFF
109 };
110
111 /*! Port 1 Direction Register */
112 config GpioBits8PxDir_t P1DIR = {
113 Bit0 : BIT0_OFF,
114 Bit1 : BIT1_OFF,
115 Bit2 : BIT2_OFF,
116 Bit3 : BIT3_OFF,
117 Bit4 : BIT4_OFF,
118 Bit5 : BIT5_OFF,
119 Bit6 : BIT6_OFF,
120 Bit7 : BIT7_OFF
121 };
122
123 /*! Port 1 Resistor Enable Register */
124 config GpioBits8PxRen_t P1REN = {
125 Bit0 : BIT0_OFF,
126 Bit1 : BIT1_OFF,
127 Bit2 : BIT2_OFF,
128 Bit3 : BIT3_OFF,
129 Bit4 : BIT4_OFF,
130 Bit5 : BIT5_OFF,
131 Bit6 : BIT6_OFF,
132 Bit7 : BIT7_OFF
133 };
134
135 /*! Port 1 Interrupt Edge Select Register */
136 config GpioBits8PxIes_t P1IES = {
137 Bit0 : BIT0_OFF,
138 Bit1 : BIT1_OFF,
139 Bit2 : BIT2_OFF,
140 Bit3 : BIT3_OFF,
141 Bit4 : BIT4_OFF,
142 Bit5 : BIT5_OFF,
143 Bit6 : BIT6_OFF,
144 Bit7 : BIT7_OFF
145 };
146
147 /*! Port 1 Interrupt Flag Register */
148 config GpioBits8PxIfg_t P1IFG = {
149 Bit0 : BIT0_OFF,
150 Bit1 : BIT1_OFF,
151 Bit2 : BIT2_OFF,
152 Bit3 : BIT3_OFF,
153 Bit4 : BIT4_OFF,
154 Bit5 : BIT5_OFF,
155 Bit6 : BIT6_OFF,
156 Bit7 : BIT7_OFF
157 };
158
159 /*! Port 1 Interrupt Enable Register */
160 config GpioBits8PxIe_t P1IE = {
161 Bit0 : BIT0_OFF,
162 Bit1 : BIT1_OFF,
163 Bit2 : BIT2_OFF,
164 Bit3 : BIT3_OFF,
165 Bit4 : BIT4_OFF,
166 Bit5 : BIT5_OFF,
167 Bit6 : BIT6_OFF,
168 Bit7 : BIT7_OFF
169 };
170
171 /*! Port 2 Output Register */
172 config GpioBits8PxOut_t P2OUT = {
173 Bit0 : BIT0_OFF,
174 Bit1 : BIT1_OFF,
175 Bit2 : BIT2_OFF,
176 Bit3 : BIT3_OFF,
177 Bit4 : BIT4_OFF,
178 Bit5 : BIT5_OFF,
179 Bit6 : BIT6_OFF,
180 Bit7 : BIT7_OFF
181 };
182
183 /*! Port 2 Port Select Register */
184 config GpioBits8PxSel_t P2SEL = {
185 Bit0 : BIT0_OFF,
186 Bit1 : BIT1_OFF,
187 Bit2 : BIT2_OFF,
188 Bit3 : BIT3_OFF,
189 Bit4 : BIT4_OFF,
190 Bit5 : BIT5_OFF,
191 Bit6 : BIT6,
192 Bit7 : BIT7
193 };
194
195 /*! Port 2 Port Select 2 Register */
196 config GpioBits8PxSel2_t P2SEL2 = {
197 Bit0 : BIT0_OFF,
198 Bit1 : BIT1_OFF,
199 Bit2 : BIT2_OFF,
200 Bit3 : BIT3_OFF,
201 Bit4 : BIT4_OFF,
202 Bit5 : BIT5_OFF,
203 Bit6 : BIT6_OFF,
204 Bit7 : BIT7_OFF
205 };
206
207 /*! Port 2 Direction Register */
208 config GpioBits8PxDir_t P2DIR = {
209 Bit0 : BIT0_OFF,
210 Bit1 : BIT1_OFF,
211 Bit2 : BIT2_OFF,
212 Bit3 : BIT3_OFF,
213 Bit4 : BIT4_OFF,
214 Bit5 : BIT5_OFF,
215 Bit6 : BIT6_OFF,
216 Bit7 : BIT7_OFF
217 };
218
219 /*! Port 2 Resistor Enable Register */
220 config GpioBits8PxRen_t P2REN = {
221 Bit0 : BIT0_OFF,
222 Bit1 : BIT1_OFF,
223 Bit2 : BIT2_OFF,
224 Bit3 : BIT3_OFF,
225 Bit4 : BIT4_OFF,
226 Bit5 : BIT5_OFF,
227 Bit6 : BIT6_OFF,
228 Bit7 : BIT7_OFF
229 };
230
231 /*! Port 2 Interrupt Edge Select Register */
232 config GpioBits8PxIes_t P2IES = {
233 Bit0 : BIT0_OFF,
234 Bit1 : BIT1_OFF,
235 Bit2 : BIT2_OFF,
236 Bit3 : BIT3_OFF,
237 Bit4 : BIT4_OFF,
238 Bit5 : BIT5_OFF,
239 Bit6 : BIT6_OFF,
240 Bit7 : BIT7_OFF
241 };
242
243 /*! Port 2 Interrupt Flag Register */
244 config GpioBits8PxIfg_t P2IFG = {
245 Bit0 : BIT0_OFF,
246 Bit1 : BIT1_OFF,
247 Bit2 : BIT2_OFF,
248 Bit3 : BIT3_OFF,
249 Bit4 : BIT4_OFF,
250 Bit5 : BIT5_OFF,
251 Bit6 : BIT6_OFF,
252 Bit7 : BIT7_OFF
253 };
254
255 /*! Port 2 Interrupt Enable Register */
256 config GpioBits8PxIe_t P2IE = {
257 Bit0 : BIT0_OFF,
258 Bit1 : BIT1_OFF,
259 Bit2 : BIT2_OFF,
260 Bit3 : BIT3_OFF,
261 Bit4 : BIT4_OFF,
262 Bit5 : BIT5_OFF,
263 Bit6 : BIT6_OFF,
264 Bit7 : BIT7_OFF
265 };
266 }