1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * Universal Serial Communication Interface
14 */
15 metaonly interface IUSCI_I2C inherits IUSCI {
16
17
18
19
20
21 /*! Own addressing mode select */
22 enum UCA10_t {
23 UCA10_OFF = 0x00, /*! Own address is a 7-bit address */
24 UCA10 = 0x80 /*! Own address is a 10-bit address */
25 };
26
27 /*! Slave addressing mode select */
28 enum UCSLA10_t {
29 UCSLA10_OFF = 0x00, /*! Address slave with 7-bit address */
30 UCSLA10 = 0x40 /*! Address slave with 10-bit address */
31 };
32
33 /*! Multi-master environment select */
34 enum UCMM_t {
35 UCMM_OFF = 0x00, /*! Single master environment. There is no other master in the system. The address compare unit is disabled. */
36 UCMM = 0x20 /*! Multi master environment */
37 };
38
39 /*! Master mode select */
40 enum UCMST_t {
41 UCMST_OFF = 0x00, /*! Slave mode */
42 UCMST = 0x40 /*! Master mode */
43 };
44
45 /*! USCI clock source select. These bits select the BRCLK source clock. */
46 enum UCSSEL_I2C_t {
47 UCSSEL_0 = 0x00, /*! UCLK */
48 UCSSEL_1 = 0x01, /*! ACLK */
49 UCSSEL_2 = 0x02 /*! SMCLK */
50
51 };
52
53 /*! Transmitter/Receiver */
54 enum UCTR_t {
55 UCTR_OFF = 0x00, /*! Receiver */
56 UCTR = 0x10 /*! Transmitter */
57 };
58
59 /*! Transmit a NACK */
60 enum UCTXNACK_t {
61 UCTXNACK_OFF = 0x00, /*! Acknowledge normally */
62 UCTXNACK = 0x08 /*! Generate NACK */
63 };
64
65 /*! Transmit STOP condition in master mode */
66 enum UCTXSTP_t {
67 UCTXSTP_OFF = 0x00, /*! No STOP generated */
68 UCTXSTP = 0x10 /*! Generate STOP */
69 };
70
71 /*! Transmit START condition in master mode */
72 enum UCTXSTT_t {
73 UCTXSTT_OFF = 0x00, /*! Do not generate START condition */
74 UCTXSTT = 0x10 /*! Generate START condition */
75 };
76
77 /*! SCL low */
78 enum UCSCLLOW_t {
79 UCSCLLOW_OFF = 0x00, /*! SCL is not held low */
80 UCSCLLOW = 0x10 /*! SCL is held low */
81 };
82
83 /*! General call address received */
84 enum UCGC_t {
85 UCGC_OFF = 0x00, /*! No general call address received */
86 UCGC = 0x10 /*! General call address received */
87 };
88
89 /*! Bus busy */
90 enum UCBBUSY_t {
91 UCBBUSY_OFF = 0x00, /*! Bus inactive */
92 UCBBUSY = 0x10 /*! Bus busy */
93 };
94
95 /*! Not-acknowledge received interrupt flag */
96 enum UCNACKIFG_t {
97 UCNACKIFG_OFF = 0x00, /*! No interrupt pending */
98 UCNACKIFG = 0x10 /*! Interrupt pending */
99 };
100
101 /*! Stop condition interrupt flag */
102 enum UCSTPIFG_t {
103 UCSTPIFG_OFF = 0x00, /*! No interrupt pending */
104 UCSTPIFG = 0x10 /*! Interrupt pending */
105 };
106
107 /*! Start condition interrupt flag */
108 enum UCSTTIFG_t {
109 UCSTTIFG_OFF = 0x00, /*! No interrupt pending */
110 UCSTTIFG = 0x10 /*! Interrupt pending */
111 };
112
113 /*! Arbitration lost interrupt flag */
114 enum UCALIFG_t {
115 UCALIFG_OFF = 0x00, /*! No interrupt pending */
116 UCALIFG = 0x10 /*! Interrupt pending */
117 };
118
119 /*! General call response enable */
120 enum UCGCEN_t {
121 UCGCEN_OFF = 0x00, /*! Do not respond to a general call */
122 UCGCEN = 0x80 /*! Respond to a general call */
123 };
124
125 struct UCxCTL0_t {
126 UCA10_t UCA10; /*! Own addressing mode select
127 * 0 Own address is a 7-bit address
128 * 1 Own address is a 10-bit address */
129 UCSLA10_t UCSLA10; /*! Slave addressing mode select
130 * 0 Address slave with 7-bit address
131 * 1 Address slave with 10-bit address */
132 UCMM_t UCMM; /*! Multi-master environment select
133 * 0 Single master environment. There is no other master in the system.
134 * The address compare unit is disabled.
135 * 1 Multi master environment */
136 UCMST_t UCMST; /*! Master mode select. When a master looses arbitration in a multi-master
137 *environment (UCMM = 1) the UCMST bit is automatically cleared and the
138 *module acts as slave.
139 * 0 Slave mode
140 * 1 Master mode */
141 UCMODE_SYNC_t UCMODE; /*! USCI Mode. The UCMODEx bits select the synchronous mode when
142 *UCSYNC = 1.
143 * 00 3-pin SPI
144 * 01 4-pin SPI (master/slave enabled if STE = 1)
145 * 10 4-pin SPI (master/slave enabled if STE = 0)
146 * 11 I2C mode */
147 UCSYNC_t UCSYNC; /*! Synchronous mode enable
148 * 0 Asynchronous mode
149 * 1 Synchronous mode */
150 }
151
152 struct UCxCTL1_t {
153 UCSSEL_I2C_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
154 * 00 UCLKI
155 * 01 ACLK
156 * 10 SMCLK
157 * 11 SMCLK */
158 UCTR_t UCTR; /*! Transmitter/Receiver
159 * 0 Receiver
160 * 1 Transmitter */
161 UCTXNACK_t UCTXNACK; /*! Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
162 *transmitted.
163 * 0 Acknowledge normally
164 * 1 Generate NACK */
165 UCTXSTP_t UCTXSTP; /*! Transmit STOP condition in master mode. Ignored in slave mode. In
166 *master receiver mode the STOP condition is preceded by a NACK.
167 *UCTXSTP is automatically cleared after STOP is generated.
168 * 0 No STOP generated
169 * 1 Generate STOP */
170 UCTXSTT_t UCTXSTT; /*! Transmit START condition in master mode. Ignored in slave mode. In
171 *master receiver mode a repeated START condition is preceded by a
172 *NACK. UCTXSTT is automatically cleared after START condition and
173 *address information is transmitted.
174 *Ignored in slave mode.
175 * 0 Do not generate START condition
176 * 1 Generate START condition */
177 UCSWRST_t UCSWRST; /*! Software reset enable
178 * 0 Disabled. USCI reset released for operation.
179 * 1 Enabled. USCI logic held in reset state. */
180 }
181
182 struct UCxSTAT_t {
183 UCSCLLOW_t UCSCLLOW; /*! SCL low
184 * 0 SCL is not held low
185 * 1 SCL is held low */
186 UCGC_t UCGC; /*! General call address received. UCGC is automatically cleared when a
187 *START condition is received.
188 * 0 No general call address received
189 * 1 General call address received */
190 UCBBUSY_t UCBBUSY; /*! Bus busy
191 * 0 Bus inactive
192 * 1 Bus busy */
193 UCNACKIFG_t UCNACKIFG; /*! Not-acknowledge received interrupt flag. UCNACKIFG is automatically
194 *cleared when a START condition is received.
195 * 0 No interrupt pending
196 * 1 Interrupt pending */
197 UCSTPIFG_t UCSTPIFG; /*! Stop condition interrupt flag. UCSTPIFG is automatically cleared when a
198 *START condition is received.
199 * 0 No interrupt pending
200 * 1 Interrupt pending */
201 UCSTTIFG_t UCSTTIFG; /*! Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP
202 *condition is received.
203 * 0 No interrupt pending
204 * 1 Interrupt pending */
205 UCALIFG_t UCALIFG; /*! Arbitration lost interrupt flag
206 * 0 No interrupt pending
207 * 1 Interrupt pending */
208 }
209
210 struct UCBxI2COA_t {
211 UCGCEN_t UCGCEN; /*! General call response enable
212 * 0 Do not respond to a general call
213 * 1 Respond to a general call */
214 UChar I2COA; /*! I2C own address. The I2COAx bits contain the local address of the USCI_Bx
215 *I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is
216 *the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB. */
217 }
218
219 instance:
220 /*!
221 * ======== getUCBxI2CSA ========
222 * Returns UCBxI2CSA register value based on which module
223 *
224 * @see #getUCBxI2CSA
225 */
226 Bits8 getUCBxI2CSA();
227
228 /*!
229 * ======== setUCBxI2CSA ========
230 * Sets UCxxI2CSA register value based on which module
231 *
232 * @see #setUCBxI2CSA
233 */
234 void setUCBxI2CSA(Bits8 value);
235 }