1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Universal Serial Interface
16 */
17 metaonly module USI inherits IUSI {
18 19 20
21 create(IClock.Instance clock);
22
23 instance:
24 /*! @_nodoc */
25 config IClock.Instance clock;
26
27 /*! USI Control Register 0 */
28 config USICTL0_t USICTL0 = {
29 USIPE7 : USIPE7_OFF,
30 USIPE6 : USIPE6_OFF,
31 USIPE5 : USIPE5_OFF,
32 USILSB : USILSB_OFF,
33 USIMST : USIMST_OFF,
34 USIGE : USIGE_OFF,
35 USIOE : USIOE_OFF,
36 USISWRST : USISWRST,
37 };
38
39 /*! USI Control Register 1 */
40 config USICTL1_t USICTL1 = {
41 USICKPH : USICKPH_OFF,
42 USII2C : USII2C_OFF,
43 USISTTIE : USISTTIE_OFF,
44 USIIE : USIIE_OFF,
45 USIAL : USIAL_OFF,
46 USISTP : USISTP_OFF,
47 USISTTIFG : USISTTIFG_OFF,
48 USIIFG : USIIFG,
49 };
50
51 /*! USI Clock Control Register */
52 config USICKCTL_t USICKCTL = {
53 USIDIV : USIDIV_0,
54 USISSEL : USISSEL_0,
55 USICKPL : USICKPL_OFF,
56 USISWCLK : USISWCLK_OFF,
57 };
58
59 /*! USI Bit Counter Register */
60 config USICNT_t USICNT = {
61 USISCLREL : USISCLREL_OFF,
62 USI16B : USI16B_OFF,
63 USIIFGCC : USIIFGCC_OFF,
64 USICNT4 : USICNT4_OFF,
65 USICNT3 : USICNT3_OFF,
66 USICNT2 : USICNT2_OFF,
67 USICNT1 : USICNT1_OFF,
68 USICNT0 : USICNT0_OFF,
69 };
70
71 /*! Determine if each Register needs to be forced set or not */
72 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
73 [
74 { register : "USICTL0" , regForceSet : false },
75 { register : "USICTL1" , regForceSet : false },
76 { register : "USICKCTL" , regForceSet : false },
77 { register : "USICNT" , regForceSet : false }
78 ];
79 }