1 /*
2 * Copyright (c) 2012 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITI811X.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITI811X ========
21 * An interface implemented by all TI811X devices
22 *
23 * This interface is defined to factor common data about all TI811X type
24 * devices into a single place; they all have the same internal memory.
25 */
26 metaonly interface ITI811X inherits ti.catalog.ICpuDataSheet
27 {
28 config long cacheSizeL1[string] = [
29 ["0k", 0x0000],
30 ["4k", 0x1000],
31 ["8k", 0x2000],
32 ["16k", 0x4000],
33 ["32k", 0x8000],
34 ];
35
36 config long cacheSizeL2[string] = [
37 ["0k", 0x00000],
38 ["32k", 0x08000],
39 ["64k", 0x10000],
40 ["128k",0x20000],
41 ["256k",0x40000],
42 ];
43
44 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
45 ['l1PMode',{desc:"L1P Cache",
46 base:0x10E00000,
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "32k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 base:0x10F00000,
57 map : [["0k",0x0000],
58 ["4k",0x1000],
59 ["8k",0x2000],
60 ["16k",0x4000],
61 ["32k",0x8000]],
62 defaultValue: "32k",
63 memorySection: "L1DSRAM"}],
64
65 ['l2Mode',{desc:"L2 Cache",
66 base:0x10800000,
67 map : [["0k",0x0000],
68 ["32k",0x8000],
69 ["64k",0x10000],
70 ["128k",0x20000],
71 ["256k",0x40000]],
72 defaultValue: "0k",
73 memorySection: "IRAM"}],
74
75 ];
76
77 instance:
78 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 override config string cpuCore = "674";
85 override config string isa = "674";
86 override config string cpuCoreRevision = "1.0";
87
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89
90 ["IRAM", {
91 comment: "Internal 256KB L2 memory",
92 name: "IRAM",
93 base: 0x10800000,
94 len: 0x40000,
95 space: "code/data",
96 access: "RWX"
97 }],
98
99 ["L1PSRAM", {
100 comment: "Internal 32KB L1 program memory",
101 name: "L1PSRAM",
102 base: 0x10E00000,
103 len: 0x8000,
104 space: "code",
105 access: "RWX"
106 }],
107
108 ["L1DSRAM", {
109 comment: "Internal 32KB L1 data memory",
110 name: "L1DSRAM",
111 base: 0x10F00000,
112 len: 0x8000,
113 space: "data",
114 access: "RW"
115 }],
116
117 ["OCMC", {
118 comment: "OCMC (On-chip RAM) (128KB)",
119 name: "OCMC",
120 base: 0x40300000,
121 len: 0x20000,
122 space: "code/data",
123 access: "RWX"
124 }],
125 ];
126 };
127 /*
128 * @(#) ti.catalog.c6000; 1, 0, 0, 0,384; 2-10-2012 12:08:51; /db/ztree/library/trees/platform/platform-n14x/src/
129 */
130