1 2 3 4 5 6 7 8 9 10 11
12
13 /*!
14 * ======== ISVS ========
15 * MSP430 ISVS interface
16 */
17 metaonly interface ISVS inherits xdc.platform.IPeripheral {
18
19 /*! VLD3 Bit */
20 enum VLD3_t {
21 VLD3_OFF = 0x00,
22 VLD3 = 0x80
23 };
24 /*! VLD2 Bit */
25 enum VLD2_t {
26 VLD2_OFF = 0x00,
27 VLD2 = 0x40
28 };
29 /*! VLD1 Bit */
30 enum VLD1_t {
31 VLD1_OFF = 0x00,
32 VLD1 = 0x20
33 };
34 /*! VLD0 Bit */
35 enum VLD0_t {
36 VLD0_OFF = 0x00,
37 VLD0 = 0x10
38 };
39 /*! PORON Bit */
40 enum PORON_t {
41 PORON_OFF = 0x00, /*! SVSFG does not cause a POR */
42 PORON = 0x08 /*! SVSFG causes a POR */
43 };
44 /*! SVSON Bit */
45 enum SVSON_t {
46 SVSON_OFF = 0x00,
47 SVSON = 0x04
48 };
49 /*! SVSOP Bit */
50 enum SVSOP_t {
51 SVSOP_OFF = 0x00,
52 SVSOP = 0x02
53 };
54 /*! SVSFG Bit */
55 enum SVSFG_t {
56 SVSFG_OFF = 0x00,
57 SVSFG = 0x01
58 };
59
60 /*!
61 * ======== ForceSetDefaultRegister_t ========
62 * Force Set Default Register
63 *
64 * Type to store if each register needs to be forced initialized
65 * even if the register is in default state.
66 *
67 * @see #ForceSetDefaultRegister_t
68 */
69 struct ForceSetDefaultRegister_t {
70 String register;
71 Bool regForceSet;
72 }
73
74 instance:
75
76 }