1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.communication.USI as USI;
13
14 /*!
15 * ======== GPIO for MSP430G2x02 ========
16 * MSP430 General Purpose Input Output Ports
17 */
18 metaonly module GPIO_MSP430G2x02 inherits IGPIO {
19 /*!
20 * ======== create ========
21 * Create an instance of this peripheral.
22 */
23 create(USI.Instance usi);
24
25 instance:
26 /*! @_nodoc */
27 config USI.Instance usi;
28
29 /*! Define an array to describe all device pins. The 1st dimension
30 * denotes the port, the second the pin on that port. On an
31 * MSP430G2x02 device, there are 8 + 8 = 16 pins total.
32 */
33
34 35
36 37
38 config DevicePin_t devicePins[2][8];
39
40 /*! Implementation of Device Pin Functional Configuration */
41 override config DevicePinFunctionSetting_t devicePinSetting[2][8];
42
43 /*! Determine if each Register needs to be forced set or not */
44 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
45 [
46 { register : "P1OUT" , regForceSet : true },
47 { register : "P1SEL" , regForceSet : false },
48 { register : "P1SEL2", regForceSet : false },
49 { register : "P1DIR" , regForceSet : false },
50 { register : "P1REN" , regForceSet : false },
51 { register : "P1IES" , regForceSet : true },
52 { register : "P1IFG" , regForceSet : true },
53 { register : "P1IE" , regForceSet : false },
54 { register : "P2OUT" , regForceSet : true },
55 { register : "P2SEL" , regForceSet : false },
56 { register : "P2SEL2", regForceSet : false },
57 { register : "P2DIR" , regForceSet : false },
58 { register : "P2REN" , regForceSet : false },
59 { register : "P2IES" , regForceSet : true },
60 { register : "P2IFG" , regForceSet : true },
61 { register : "P2IE" , regForceSet : false }
62 ];
63
64 65 66 67 68 69
70
71 /*! Port 1 Output Register */
72 config GpioBits8PxOut_t P1OUT = {
73 Bit0 : BIT0_OFF,
74 Bit1 : BIT1_OFF,
75 Bit2 : BIT2_OFF,
76 Bit3 : BIT3_OFF,
77 Bit4 : BIT4_OFF,
78 Bit5 : BIT5_OFF,
79 Bit6 : BIT6_OFF,
80 Bit7 : BIT7_OFF
81 };
82
83 /*! Port 1 Port Select Register */
84 config GpioBits8PxSel_t P1SEL = {
85 Bit0 : BIT0_OFF,
86 Bit1 : BIT1_OFF,
87 Bit2 : BIT2_OFF,
88 Bit3 : BIT3_OFF,
89 Bit4 : BIT4_OFF,
90 Bit5 : BIT5_OFF,
91 Bit6 : BIT6_OFF,
92 Bit7 : BIT7_OFF
93 };
94
95 /*! Port 1 Port Select 2 Register */
96 config GpioBits8PxSel2_t P1SEL2 = {
97 Bit0 : BIT0_OFF,
98 Bit1 : BIT1_OFF,
99 Bit2 : BIT2_OFF,
100 Bit3 : BIT3_OFF,
101 Bit4 : BIT4_OFF,
102 Bit5 : BIT5_OFF,
103 Bit6 : BIT6_OFF,
104 Bit7 : BIT7_OFF
105 };
106
107 /*! Port 1 Direction Register */
108 config GpioBits8PxDir_t P1DIR = {
109 Bit0 : BIT0_OFF,
110 Bit1 : BIT1_OFF,
111 Bit2 : BIT2_OFF,
112 Bit3 : BIT3_OFF,
113 Bit4 : BIT4_OFF,
114 Bit5 : BIT5_OFF,
115 Bit6 : BIT6_OFF,
116 Bit7 : BIT7_OFF
117 };
118
119 /*! Port 1 Resistor Enable Register */
120 config GpioBits8PxRen_t P1REN = {
121 Bit0 : BIT0_OFF,
122 Bit1 : BIT1_OFF,
123 Bit2 : BIT2_OFF,
124 Bit3 : BIT3_OFF,
125 Bit4 : BIT4_OFF,
126 Bit5 : BIT5_OFF,
127 Bit6 : BIT6_OFF,
128 Bit7 : BIT7_OFF
129 };
130
131 /*! Port 1 Interrupt Edge Select Register */
132 config GpioBits8PxIes_t P1IES = {
133 Bit0 : BIT0_OFF,
134 Bit1 : BIT1_OFF,
135 Bit2 : BIT2_OFF,
136 Bit3 : BIT3_OFF,
137 Bit4 : BIT4_OFF,
138 Bit5 : BIT5_OFF,
139 Bit6 : BIT6_OFF,
140 Bit7 : BIT7_OFF
141 };
142
143 /*! Port 1 Interrupt Flag Register */
144 config GpioBits8PxIfg_t P1IFG = {
145 Bit0 : BIT0_OFF,
146 Bit1 : BIT1_OFF,
147 Bit2 : BIT2_OFF,
148 Bit3 : BIT3_OFF,
149 Bit4 : BIT4_OFF,
150 Bit5 : BIT5_OFF,
151 Bit6 : BIT6_OFF,
152 Bit7 : BIT7_OFF
153 };
154
155 /*! Port 1 Interrupt Enable Register */
156 config GpioBits8PxIe_t P1IE = {
157 Bit0 : BIT0_OFF,
158 Bit1 : BIT1_OFF,
159 Bit2 : BIT2_OFF,
160 Bit3 : BIT3_OFF,
161 Bit4 : BIT4_OFF,
162 Bit5 : BIT5_OFF,
163 Bit6 : BIT6_OFF,
164 Bit7 : BIT7_OFF
165 };
166
167 /*! Port 2 Output Register */
168 config GpioBits8PxOut_t P2OUT = {
169 Bit0 : BIT0_OFF,
170 Bit1 : BIT1_OFF,
171 Bit2 : BIT2_OFF,
172 Bit3 : BIT3_OFF,
173 Bit4 : BIT4_OFF,
174 Bit5 : BIT5_OFF,
175 Bit6 : BIT6_OFF,
176 Bit7 : BIT7_OFF
177 };
178
179 /*! Port 2 Port Select Register */
180 config GpioBits8PxSel_t P2SEL = {
181 Bit0 : BIT0_OFF,
182 Bit1 : BIT1_OFF,
183 Bit2 : BIT2_OFF,
184 Bit3 : BIT3_OFF,
185 Bit4 : BIT4_OFF,
186 Bit5 : BIT5_OFF,
187 Bit6 : BIT6,
188 Bit7 : BIT7
189 };
190
191 /*! Port 2 Port Select 2 Register */
192 config GpioBits8PxSel2_t P2SEL2 = {
193 Bit0 : BIT0_OFF,
194 Bit1 : BIT1_OFF,
195 Bit2 : BIT2_OFF,
196 Bit3 : BIT3_OFF,
197 Bit4 : BIT4_OFF,
198 Bit5 : BIT5_OFF,
199 Bit6 : BIT6_OFF,
200 Bit7 : BIT7_OFF
201 };
202
203 /*! Port 2 Direction Register */
204 config GpioBits8PxDir_t P2DIR = {
205 Bit0 : BIT0_OFF,
206 Bit1 : BIT1_OFF,
207 Bit2 : BIT2_OFF,
208 Bit3 : BIT3_OFF,
209 Bit4 : BIT4_OFF,
210 Bit5 : BIT5_OFF,
211 Bit6 : BIT6_OFF,
212 Bit7 : BIT7_OFF
213 };
214
215 /*! Port 2 Resistor Enable Register */
216 config GpioBits8PxRen_t P2REN = {
217 Bit0 : BIT0_OFF,
218 Bit1 : BIT1_OFF,
219 Bit2 : BIT2_OFF,
220 Bit3 : BIT3_OFF,
221 Bit4 : BIT4_OFF,
222 Bit5 : BIT5_OFF,
223 Bit6 : BIT6_OFF,
224 Bit7 : BIT7_OFF
225 };
226
227 /*! Port 2 Interrupt Edge Select Register */
228 config GpioBits8PxIes_t P2IES = {
229 Bit0 : BIT0_OFF,
230 Bit1 : BIT1_OFF,
231 Bit2 : BIT2_OFF,
232 Bit3 : BIT3_OFF,
233 Bit4 : BIT4_OFF,
234 Bit5 : BIT5_OFF,
235 Bit6 : BIT6_OFF,
236 Bit7 : BIT7_OFF
237 };
238
239 /*! Port 2 Interrupt Flag Register */
240 config GpioBits8PxIfg_t P2IFG = {
241 Bit0 : BIT0_OFF,
242 Bit1 : BIT1_OFF,
243 Bit2 : BIT2_OFF,
244 Bit3 : BIT3_OFF,
245 Bit4 : BIT4_OFF,
246 Bit5 : BIT5_OFF,
247 Bit6 : BIT6_OFF,
248 Bit7 : BIT7_OFF
249 };
250
251 /*! Port 2 Interrupt Enable Register */
252 config GpioBits8PxIe_t P2IE = {
253 Bit0 : BIT0_OFF,
254 Bit1 : BIT1_OFF,
255 Bit2 : BIT2_OFF,
256 Bit3 : BIT3_OFF,
257 Bit4 : BIT4_OFF,
258 Bit5 : BIT5_OFF,
259 Bit6 : BIT6_OFF,
260 Bit7 : BIT7_OFF
261 };
262 }