1 /*
2 * Copyright (c) 2011 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Kepler.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 metaonly module Kepler inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 config long cacheSizeL2[string] = [
32 ["0k", 0x000000],
33 ["32k", 0x008000],
34 ["64k", 0x010000],
35 ["128k", 0x020000],
36 ["256k", 0x040000],
37 ["512k", 0x080000],
38 ["1024k", 0x100000]
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
42 ['l1PMode',
43 {desc:"L1P Cache",
44 base: 0x00E00000,
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "32k",
51 memorySection: "L1PSRAM"
52 }
53 ],
54 ['l1DMode',
55 {desc:"L1D Cache",
56 base: 0x00F00000,
57 map : [["0k",0x0000],
58 ["4k",0x1000],
59 ["8k",0x2000],
60 ["16k",0x4000],
61 ["32k",0x8000]],
62 defaultValue: "32k",
63 memorySection: "L1DSRAM"
64 }
65 ],
66 ['l2Mode',
67 {desc:"L2 Cache",
68 base: 0x00800000,
69 map : [["0k",0x0000],
70 ["32k",0x8000],
71 ["64k",0x10000],
72 ["128k", 0x020000],
73 ["256k", 0x040000],
74 ["512k", 0x080000],
75 ["1024k", 0x100000]],
76 defaultValue: "0k",
77 memorySection: "L2SRAM"
78 }
79 ],
80 ];
81
82 instance:
83
84 override config string cpuCore = "6600";
85 override config string isa = "66";
86 override config string cpuCoreRevision = "1.0";
87
88 override config int minProgUnitSize = 1;
89 override config int minDataUnitSize = 1;
90 override config int dataWordSize = 4;
91
92 /*!
93 * ======== memMap ========
94 * The default memory map for this device
95 */
96 config xdc.platform.IPlatform.Memory memMap[string] = [
97 ["L2SRAM", {
98 comment: "1MB L2 SRAM/CACHE",
99 name: "L2SRAM",
100 base: 0x00800000,
101 len: 0x00100000,
102 space: "code/data",
103 access: "RWX"
104 }],
105
106 ["L1PSRAM", {
107 comment: "32KB RAM/CACHE L1 program memory",
108 name: "L1PSRAM",
109 base: 0x00E00000,
110 len: 0x00008000,
111 space: "code",
112 access: "RWX"
113 }],
114
115 ["L1DSRAM", {
116 comment: "32KB RAM/CACHE L1 data memory",
117 name: "L1DSRAM",
118 base: 0x00F00000,
119 len: 0x00008000,
120 space: "data",
121 access: "RW"
122 }],
123
124 ["MSMCSRAM", {
125 comment: "6MB MSMC SRAM",
126 name: "MSMCSRAM",
127 base: 0x0C000000,
128 len: 0x00600000,
129 space: "code/data",
130 access: "RWX"
131 }],
132 ];
133 };
134 /*
135 * @(#) ti.catalog.c6000; 1, 0, 0, 0,378; 11-9-2011 11:59:56; /db/ztree/library/trees/platform/platform-n08x/src/
136 */
137