1    /*
     2     *  Copyright (c) 2011 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITI8168.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITI8168 ========
    20     *  An interface implemented by all TI8168 devices
    21     *
    22     *  This interface is defined to factor common data about all TI8168 type devices
    23     *  into a single place; they all have the same internal memory.
    24     */
    25    metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet
    26    {
    27    instance:
    28        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    29        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
    30        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
    31    
    32        override config string cpuCore           = "CM3";
    33        override config string isa               = "v7M";
    34        override config string cpuCoreRevision   = "1.0";
    35        override config int    minProgUnitSize   = 1;
    36        override config int    minDataUnitSize   = 1;
    37        override config int    dataWordSize      = 4;
    38    
    39        /*!
    40         *  ======== memMap ========
    41         *  The memory map returned be getMemoryMap().
    42         */
    43        config xdc.platform.IPlatform.Memory memMap[string] = [
    44    
    45            /*
    46             * AMMU mapped L2 BOOT virtual address
    47             * Physical address is 0x5502_0000, virt is 0x00000000
    48             * Reset vectors and other boot code is placed here.
    49             *
    50             * Note that actual L2 RAM is 256K starting at 0x5502_0000.
    51             * The first 16K is reserved for reset vectors (i.e. L2_BOOT).
    52             * The remaining 240K is placed in the L2_RAM definition.
    53             */
    54            ["L2_BOOT", {
    55                name: "L2_BOOT",
    56                base: 0x00000000,
    57                len:  0x4000
    58            }],
    59    
    60            /*
    61             * AMMU mapped L2 RAM virtual address
    62             * Physical address is 0x5502_4000, virt is 0x2000_4000
    63             *
    64             * Note that actual L2 RAM is 256K starting at 0x5502_0000.
    65             * The first 16K is reserved for reset vectors (i.e. L2_BOOT).
    66             * The remaining 240K is placed in the L2_RAM definition.
    67             */
    68            ["L2_RAM", {
    69                name: "L2_RAM",
    70                base: 0x20004000,
    71                len:  0x3C000
    72            }],
    73    
    74            /*
    75             * OCMC (On-chip RAM) Bank 0
    76             * Physical address is 0x40300000
    77             * Size is 256K
    78             */
    79            ["OCMC_0", {
    80                name: "OCMC_0",
    81                base: 0x00300000,
    82                len:  0x40000
    83            }],
    84    
    85            /*
    86             * OCMC (On-chip RAM) Bank 1
    87             * Physical address is 0x40400000
    88             * Size is 256K
    89             */
    90            ["OCMC_1", {
    91                name: "OCMC_1",
    92                base: 0x00400000,
    93                len:  0x40000
    94            }],
    95        ];
    96    };
    97    /*
    98     *  @(#) ti.catalog.arm.cortexm3; 1, 0, 0,136; 11-9-2011 11:59:28; /db/ztree/library/trees/platform/platform-n08x/src/
    99     */
   100