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12 /*!
13 * ======== IUSI ========
14 * Universal Serial Interface
15 */
16 metaonly interface IUSI inherits xdc.platform.IPeripheral {
17 18 19
20
21 /*! USI SDI/SDA port enable.
22 *Input in SPI mode, input or open drain output in I2C mode. */
23 enum USIPE7_t {
24 USIPE7_OFF = 0x00, /*! USI function disabled */
25 USIPE7 = 0x80 /*! USI function enabled */
26 };
27
28 /*! USI SDO/SCL port enable.
29 *Output in SPI mode, input or open drain output in I2C mode. */
30 enum USIPE6_t {
31 USIPE6_OFF = 0x00, /*! USI function disabled */
32 USIPE6 = 0x40 /*! USI function enabled */
33 };
34
35 /*! USI SCLK port enable.
36 *Input in SPI slave mode, or I2C mode, output in SPI master mode. */
37 enum USIPE5_t {
38 USIPE5_OFF = 0x00, /*! USI function disabled */
39 USIPE5 = 0x20 /*! USI function enabled */
40 };
41
42 /*! LSB first select. This bit controls the direction of the receive and transmit shift register. */
43 enum USILSB_t {
44 USILSB_OFF = 0x00, /*! MSB first */
45 USILSB = 0x10 /*! LSB first */
46 };
47
48 /*! Master select */
49 enum USIMST_t {
50 USIMST_OFF = 0x00, /*! Slave mode */
51 USIMST = 0x08 /*! Master mode */
52 };
53
54 /*! Output latch control */
55 enum USIGE_t {
56 USIGE_OFF = 0x00, /*! Output latch enable depends on shift clock */
57 USIGE = 0x04 /*! Output latch always enabled and transparent */
58 };
59
60 /*! Data output enable */
61 enum USIOE_t {
62 USIOE_OFF = 0x00, /*! Output disabled */
63 USIOE = 0x02 /*! Output enabled */
64 };
65
66 /*! USI software reset */
67 enum USISWRST_t {
68 USISWRST_OFF = 0x00, /*! USI released for operation. */
69 USISWRST = 0x01 /*! USI logic held in reset state. */
70 };
71
72 /*! Clock phase select */
73 enum USICKPH_t {
74 USICKPH_OFF = 0x00, /*! Data is changed on the first SCLK edge and captured on the following edge. */
75 USICKPH = 0x80 /*! Data is captured on the first SCLK edge and changed on the following edge. */
76 };
77
78 /*! I2C mode enable */
79 enum USII2C_t {
80 USII2C_OFF = 0x00, /*! I2C mode disabled */
81 USII2C = 0x40 /*! I2C mode enabled */
82 };
83
84 /*! START condition interrupt-enable */
85 enum USISTTIE_t {
86 USISTTIE_OFF = 0x00, /*! Interrupt on START condition disabled */
87 USISTTIE = 0x20 /*! Interrupt on START condition enabled */
88 };
89
90 /*! USI counter interrupt enable */
91 enum USIIE_t {
92 USIIE_OFF = 0x00, /*! Interrupt disabled */
93 USIIE = 0x10 /*! Interrupt enabled */
94 };
95
96 /*! Arbitration lost */
97 enum USIAL_t {
98 USIAL_OFF = 0x00, /*! No arbitration lost condition */
99 USIAL = 0x08 /*! Arbitration lost */
100 };
101
102 /*! STOP condition received. USISTP is automatically cleared if USICNTx is
103 *loaded with a value > 0 when USIIFGCC = 0. */
104 enum USISTP_t {
105 USISTP_OFF = 0x00, /*! No STOP condition received */
106 USISTP = 0x04 /*! STOP condition received */
107 };
108
109 /*! START condition interrupt flag */
110 enum USISTTIFG_t {
111 USISTTIFG_OFF = 0x00, /*! No START condition received. No interrupt pending. */
112 USISTTIFG = 0x02 /*! START condition received. Interrupt pending. */
113 };
114
115 /*! USI counter interrupt flag. Set when the USICNTx = 0. Automatically
116 *cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. */
117 enum USIIFG_t {
118 USIIFG_OFF = 0x00, /*! No interrupt pending */
119 USIIFG = 0x01 /*! Interrupt pending */
120 };
121
122 /*! Clock divider select */
123 enum USIDIV_t {
124 USIDIV_0 = 0x00, /*! Divide by 1 */
125 USIDIV_1 = 0x20, /*! Divide by 2 */
126 USIDIV_2 = 0x40, /*! Divide by 4 */
127 USIDIV_3 = 0x60, /*! Divide by 8 */
128 USIDIV_4 = 0x80, /*! Divide by 16 */
129 USIDIV_5 = 0xA0, /*! Divide by 32 */
130 USIDIV_6 = 0xC0, /*! Divide by 64 */
131 USIDIV_7 = 0xE0 /*! Divide by 128 */
132 };
133
134 /*! Clock source select. Not used in slave mode. */
135 enum USISSEL_t {
136 USISSEL_0 = 0x00, /*! SCLK (Not used in SPI mode) */
137 USISSEL_1 = 0x04, /*! ACLK */
138 USISSEL_2 = 0x08, /*! SMCLK */
139 USISSEL_3 = 0x0C, /*! SMCLK */
140 USISSEL_4 = 0x10, /*! USISWCLK bit */
141 USISSEL_5 = 0x14, /*! TACCR0 */
142 USISSEL_6 = 0x18, /*! TACCR1 */
143 USISSEL_7 = 0x1C /*! TACCR2 (Reserved on MSP430F20xx devices) */
144 };
145
146 /*! Clock polarity select */
147 enum USICKPL_t {
148 USICKPL_OFF = 0x00, /*! Inactive state is low */
149 USICKPL = 0x02 /*! Inactive state is high */
150 };
151
152 /*! Software clock */
153 enum USISWCLK_t {
154 USISWCLK_OFF = 0x00, /*! Input clock is low */
155 USISWCLK = 0x01 /*! Input clock is high */
156 };
157
158 /*! SCL release. The SCL line is released from low to idle. USISCLREL is
159 *cleared if a START condition is detected. */
160 enum USISCLREL_t {
161 USISCLREL_OFF = 0x00, /*! SCL line is held low if USIIFG is set */
162 USISCLREL = 0x80 /*! SCL line is released */
163 };
164
165 /*! 16-bit shift register enable */
166 enum USI16B_t {
167 USI16B_OFF = 0x00, /*! 8-bit shift register mode. Low byte register USISRL is used. */
168 USI16B = 0x40 /*! 16-bit shift register mode. Both high and low byte registers USISRL
169 *and USISRH are used. USISR addresses all 16 bits simultaneously. */
170 };
171
172 /*! USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
173 *cleared automatically when USICNTx is written with a value > 0. */
174 enum USIIFGCC_t {
175 USIIFGCC_OFF = 0x00, /*! USIIFG automatically cleared on USICNTx update */
176 USIIFGCC = 0x20 /*! USIIFG is not cleared automatically */
177 };
178
179 /*! USI bit count - Bit4 */
180 enum USICNT4_t {
181 USICNT4_OFF = 0x00, /*! USI bit count */
182 USICNT4 = 0x10 /*! USI bit count */
183 };
184
185 /*! USI bit count - Bit3 */
186 enum USICNT3_t {
187 USICNT3_OFF = 0x00, /*! USI bit count */
188 USICNT3 = 0x08 /*! USI bit count */
189 };
190
191 /*! USI bit count - Bit2 */
192 enum USICNT2_t {
193 USICNT2_OFF = 0x00, /*! USI bit count */
194 USICNT2 = 0x04 /*! USI bit count */
195 };
196
197 /*! USI bit count - Bit1 */
198 enum USICNT1_t {
199 USICNT1_OFF = 0x00, /*! USI bit count */
200 USICNT1 = 0x02 /*! USI bit count */
201 };
202
203 /*! USI bit count - Bit0 */
204 enum USICNT0_t {
205 USICNT0_OFF = 0x00, /*! USI bit count */
206 USICNT0 = 0x01 /*! USI bit count */
207 };
208
209 struct USICTL0_t {
210 USIPE7_t USIPE7; /*! USI SDI/SDA port enable.
211 *Input in SPI mode, input or open drain output in I2C mode.
212 * 0 USI function disabled
213 * 1 USI function enabled */
214 USIPE6_t USIPE6; /*! USI SDO/SCL port enable.
215 *Output in SPI mode, input or open drain output in I2C mode.
216 * 0 USI function disabled
217 * 1 USI function enabled */
218 USIPE5_t USIPE5; /*! USI SCLK port enable.
219 *Input in SPI slave mode, or I2C mode, output in SPI master mode.
220 * 0 USI function disabled
221 * 1 USI function enabled */
222 USILSB_t USILSB; /*! LSB first select. This bit controls the direction of the receive and transmit shift register.
223 * 0 MSB first
224 * 1 LSB first */
225 USIMST_t USIMST; /*! Master select
226 * 0 Slave mode
227 * 1 Master mode */
228 USIGE_t USIGE; /*! Output latch control
229 * 0 Output latch enable depends on shift clock
230 * 1 Output latch always enabled and transparent */
231 USIOE_t USIOE; /*! Data output enable
232 * 0 Output disabled
233 * 1 Output enabled */
234 USISWRST_t USISWRST; /*! USI software reset
235 * 0 USI released for operation.
236 * 1 USI logic held in reset state. */
237 }
238
239 struct USICTL1_t {
240 USICKPH_t USICKPH; /*! Clock phase select
241 * 0 Data is changed on the first SCLK edge and captured on the
242 * following edge.
243 * 1 Data is captured on the first SCLK edge and changed on the
244 * following edge. */
245 USII2C_t USII2C; /*! I2C mode enable
246 * 0 I2C mode disabled
247 * 1 I2C mode enabled*/
248 USISTTIE_t USISTTIE; /*! START condition interrupt-enable
249 * 0 Interrupt on START condition disabled
250 * 1 Interrupt on START condition enabled */
251 USIIE_t USIIE; /*! USI counter interrupt enable
252 * 0 Interrupt disabled
253 * 1 Interrupt enabled */
254 USIAL_t USIAL; /*! Arbitration lost
255 * 0 No arbitration lost condition
256 * 1 Arbitration lost */
257 USISTP_t USISTP; /*! STOP condition received. USISTP is automatically cleared if USICNTx is
258 *loaded with a value > 0 when USIIFGCC = 0.
259 * 0 No STOP condition received
260 * 1 STOP condition received */
261 USISTTIFG_t USISTTIFG; /*! START condition interrupt flag
262 * 0 No START condition received. No interrupt pending.
263 * 1 START condition received. Interrupt pending. */
264 USIIFG_t USIIFG; /*! USI counter interrupt flag. Set when the USICNTx = 0. Automatically
265 *cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0.
266 * 0 No interrupt pending
267 * 1 Interrupt pending */
268 }
269
270 struct USICKCTL_t {
271 USIDIV_t USIDIV; /*! Clock divider select
272 * 000 Divide by 1
273 * 001 Divide by 2
274 * 010 Divide by 4
275 * 011 Divide by 8
276 * 100 Divide by 16
277 * 101 Divide by 32
278 * 110 Divide by 64
279 * 111 Divide by 128 */
280 USISSEL_t USISSEL; /*! Clock source select. Not used in slave mode.
281 * 000 SCLK (Not used in SPI mode)
282 * 001 ACLK
283 * 010 SMCLK
284 * 011 SMCLK
285 * 100 USISWCLK bit
286 * 101 TACCR0
287 * 110 TACCR1
288 * 111 TACCR2 (Reserved on MSP430F20xx devices) */
289 USICKPL_t USICKPL; /*! Clock polarity select
290 * 0 Inactive state is low
291 * 1 Inactive state is high */
292 USISWCLK_t USISWCLK; /*! Software clock
293 * 0 Input clock is low
294 * 1 Input clock is high */
295 }
296
297 struct USICNT_t {
298 USISCLREL_t USISCLREL; /*! SCL release. The SCL line is released from low to idle. USISCLREL is
299 * cleared if a START condition is detected.
300 * 0 SCL line is held low if USIIFG is set
301 * 1 SCL line is released */
302 USI16B_t USI16B; /*! 16-bit shift register enable
303 * 0 8-bit shift register mode. Low byte register USISRL is used.
304 * 1 16-bit shift register mode. Both high and low byte registers USISRL
305 * and USISRH are used. USISR addresses all 16 bits simultaneously.*/
306 USIIFGCC_t USIIFGCC; /*! USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
307 *cleared automatically when USICNTx is written with a value > 0.
308 * 0 USIIFG automatically cleared on USICNTx update
309 * 1 USIIFG is not cleared automatically */
310 USICNT4_t USICNT4; /*! USI bit count bit 4
311 *The USICNTx bits set the number of bits to be received or transmitted. */
312 USICNT3_t USICNT3; /*! USI bit count bit 3
313 *The USICNTx bits set the number of bits to be received or transmitted. */
314 USICNT2_t USICNT2; /*! USI bit count bit 2
315 *The USICNTx bits set the number of bits to be received or transmitted. */
316 USICNT1_t USICNT1; /*! USI bit count bit 1
317 *The USICNTx bits set the number of bits to be received or transmitted. */
318 USICNT0_t USICNT0; /*! USI bit count bit 0
319 *The USICNTx bits set the number of bits to be received or transmitted. */
320 }
321
322 /*!
323 * ======== ForceSetDefaultRegister_t ========
324 * Force Set Default Register
325 *
326 * Type to store if each register needs to be forced initialized
327 * even if the register is in default state.
328 *
329 * @see #ForceSetDefaultRegister_t
330 */
331 struct ForceSetDefaultRegister_t {
332 String register;
333 Bool regForceSet;
334 }
335
336 instance:
337
338 /*!
339 * ======== setUSIIE ========
340 * Sets USIIE register
341 *
342 * @see #setUSIIE
343 */
344 Bool setUSIIE(Bool set);
345
346 /*!
347 * ======== setUSIIE ========
348 * Gets USIIE register
349 *
350 * @see #setUSIIE
351 */
352 Bool getUSIIE();
353
354 /*!
355 * ======== setUSISTTIE ========
356 * Sets USISTTIE register
357 *
358 * @see #setUSISTTIE
359 */
360 Bool setUSISTTIE(Bool set);
361
362 /*!
363 * ======== getUSISTTIE ========
364 * Gets USISTTIE register
365 *
366 * @see #getUSISTTIE
367 */
368 Bool getUSISTTIE();
369 }