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12 /*!
13 * ======== IUSCI ========
14 * Universal Serial Communication Interface
15 */
16 metaonly interface IUSCI inherits xdc.platform.IPeripheral {
17 18 19
20
21 /*! MSB first select. Controls the direction of the receive and transmit shift register. */
22 enum UCMSB_t {
23 UCMSB_OFF = 0x00, /*! LSB first */
24 UCMSB = 0x02 /*! MSB first */
25 };
26
27 /*! Character length. Selects 7-bit or 8-bit character length. */
28 enum UC7BIT_t {
29 UC7BIT_OFF = 0x00, /*! 8-bit */
30 UC7BIT = 0x02 /*! 7-bit */
31 };
32
33 /*! Synchronous mode enable */
34 enum UCSYNC_t {
35 UCSYNC_OFF = 0x00, /*! Asynchronous mode */
36 UCSYNC = 0x02 /*! Synchronous Mode */
37 };
38
39 /*! Receive erroneous-character interrupt-enable */
40 enum UCRXEIE_t {
41 UCRXEIE_OFF = 0x00, /*! Erroneous characters rejected and UCAxRXIFG is not set */
42 UCRXEIE = 0x02 /*! Erroneous characters received will set UCAxRXIFG */
43 };
44
45 /*! Receive break character interrupt-enable */
46 enum UCBRKIE_t {
47 UCBRKIE_OFF = 0x00, /*! Received break characters do not set UCAxRXIFG. */
48 UCBRKIE = 0x02 /*! Received break characters set UCAxRXIFG. */
49 };
50
51 /*! Dormant. Puts USCI into sleep mode. */
52 enum UCDORM_t {
53 UCDORM_OFF = 0x00, /*! Not dormant. All received characters will set UCAxRXIFG. */
54 UCDORM = 0x02 /*! Dormant. Only characters that are preceded by an idle-line or with
55 * address bit set will set UCAxRXIFG. In UART mode with automatic baud
56 * rate detection only the combination of a break and synch field will set
57 * UCAxRXIFG. */
58 };
59
60 /*! Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. */
61 enum UCTXADDR_t {
62 UCTXADDR_OFF = 0x00, /*! Next frame transmitted is data */
63 UCTXADDR = 0x02 /*! Next frame transmitted is an address */
64 };
65
66 /*! Transmit break. Transmits a break with the next write to the transmit buffer.
67 * In UART mode with automatic baud rate detection 055h must be written
68 * into UCAxTXBUF to generate the required break/synch fields. Otherwise
69 * 0h must be written into the transmit buffer. */
70 enum UCTXBRK_t {
71 UCTXBRK_OFF = 0x00, /*! Next frame transmitted is not a break */
72 UCTXBRK = 0x02 /*! Next frame transmitted is a break or a break/synch */
73 };
74
75 /*! Software reset enable */
76 enum UCSWRST_t {
77 UCSWRST_OFF = 0x00, /*! Disabled. USCI reset released for operation. */
78 UCSWRST = 0x02 /*! Enabled. USCI logic held in reset state. */
79 };
80
81 /*! Listen enable. The UCLISTEN bit selects loopback mode. */
82 enum UCLISTEN_t {
83 UCLISTEN_OFF = 0x00, /*! Disabled. */
84 UCLISTEN = 0x02 /*! Enabled. UCAxTXD is internally fed back to the receiver. */
85 };
86
87 /*! Framing error flag */
88 enum UCFE_t {
89 UCFE_OFF = 0x00, /*! 0 No error */
90 UCFE = 0x02 /*! Character received with low stop bit */
91 };
92
93 /*! Overrun error flag. */
94 enum UCOE_t {
95 UCOE_OFF = 0x00, /*! No error. */
96 UCOE = 0x02 /*! Overrun error occurred. */
97 };
98
99 /*! Parity error flag. When UCPEN = 0, UCPE is read as 0. */
100 enum UCPE_t {
101 UCPE_OFF = 0x00, /*! No error. */
102 UCPE = 0x02 /*! Character received with parity error. */
103 };
104
105 /*! Break detect flag */
106 enum UCBRK_t {
107 UCBRK_OFF = 0x00, /*! No break condition */
108 UCBRK = 0x02 /*! Break condition occurred */
109 };
110
111 /*! Bit 2 Receive error flag. This bit indicates a character was received with error(s).
112 * When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
113 * set. UCRXERR is cleared when UCAxRXBUF is read. */
114 enum UCRXERR_t {
115 UCRXERR_OFF = 0x00, /*! No receive errors detected */
116 UCRXERR = 0x02 /*! Receive error detected */
117 };
118
119 /*! Address received in address-bit multiprocessor mode. */
120 enum UCADDR_t {
121 UCADDR_OFF = 0x00, /*! Received character is data */
122 UCADDR = 0x02 /*! Received character is an address */
123 };
124
125 /*! Idle line detected in idle-line multiprocessor mode. */
126 enum UCIDLE_t {
127 UCIDLE_OFF = 0x00, /*! No idle line detected */
128 UCIDLE = 0x02 /*! Idle line detected */
129 };
130
131 /*! USCI busy. This bit indicates if a transmit or receive operation is in progress. */
132 enum UCBUSY_t {
133 UCBUSY_OFF = 0x00, /*! USCI inactive */
134 UCBUSY = 0x01 /*! USCI transmitting or receiving */
135 };
136
137 /*! USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. */
138 enum UCMODE_SYNC_t {
139 UCMODE_0 = 0x00, /*! 3-Pin SPI */
140 UCMODE_1 = 0x01, /*! 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 */
141 UCMODE_2 = 0x02, /*! 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 */
142 UCMODE_3 = 0x04 /*! I2C Mode */
143 };
144
145 /*!
146 * ======== ForceSetDefaultRegister_t ========
147 * Force Set Default Register
148 *
149 * Type to store if each register needs to be forced initialized
150 * even if the register is in default state.
151 *
152 * @see #ForceSetDefaultRegister_t
153 */
154 struct ForceSetDefaultRegister_t {
155 String register;
156 Bool regForceSet;
157 }
158
159 instance:
160 /*!
161 * Stores the UCLK external clock frequency in float
162 */
163 config float UCLKHz = 1000000;
164
165 /*!
166 * ======== setUCxxBR0 ========
167 * Sets UCxxBR0 register value based on which module
168 *
169 * @see #setUCxxBR0
170 */
171 void setUCxxBR0(Bits8 value);
172
173 /*!
174 * ======== getUCxxBR0 ========
175 * Returns UCxxBR0 register value based on which module
176 *
177 * @see #getUCxxBR0
178 */
179 Bits8 getUCxxBR0();
180
181 /*!
182 * ======== setUCxxBR1 ========
183 * Sets UCxxBR1 register value based on which module
184 *
185 * @see #setUCxxBR1
186 */
187 void setUCxxBR1(Bits8 value);
188
189 /*!
190 * ======== getUCxxBR1 ========
191 * Returns UCxxBR1 register value based on which module
192 *
193 * @see #getUCxxBR1
194 */
195 Bits8 getUCxxBR1();
196
197 /*!
198 * ======== getUCxxTXIE ========
199 * Gets UCxxTXIE bit
200 *
201 * @see #getUCxxTXIE
202 */
203 Bool getUCxxTXIE();
204
205 /*!
206 * ======== setUCxxTXIE ========
207 * Sets UCxxTXIE bit
208 *
209 * @see #setUCxxTXIE
210 */
211 Bool setUCxxTXIE(Bool set);
212
213 /*!
214 * ======== getUCxxRXIE ========
215 * Gets UCxxRXIE bit
216 *
217 * @see #getUCxxRXIE
218 */
219 Bool getUCxxRXIE();
220
221 /*!
222 * ======== setUCxxRXIE ========
223 * Sets UCxxRXIE bit
224 *
225 * @see #setUCxxRXIE
226 */
227 Bool setUCxxRXIE(Bool set);
228 }