1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2008 Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12 /*!
13 * ======== ITimer_B ========
14 * MSP430 ITimer_B interface
15 */
16 metaonly interface ITimer_B inherits ITimer {
17
18 enum TBCLGRP_t {
19 TBCLGRP_0 = (0*0x100u), /* */
20 TBCLGRP_1 = (1*0x100u), /* */
21 TBCLGRP_2 = (2*0x100u), /* */
22 TBCLGRP_3 = 3*0x100u /* */
23 };
24
25 enum CNTL_t {
26 CNTL_0 = (0*0x100u), /*! 16-bit, TBR(max) = 0FFFFh */
27 CNTL_1 = (1*0x100u), /*! 12-bit, TBR(max) = 0FFFh */
28 CNTL_2 = (2*0x100u), /*! 10-bit, TBR(max) = 03FFh */
29 CNTL_3 = 3*0x100u /*! 8-bit, TBR(max) = 0FFh */
30 };
31
32 enum TBSSEL_t {
33 TBSSEL_0 = (0*0x100u), /*! TBCLK */
34 TBSSEL_1 = (1*0x100u), /*! ACLK */
35 TBSSEL_2 = (2*0x100u), /*! SMCLK */
36 TBSSEL_3 = 3*0x100u /*! INCLK */
37 };
38
39 enum TBCLR_t {
40 TBCLR_OFF = (0x0000), /* Timer A counter clear */
41 TBCLR = 0x0004 /* Timer A counter clear */
42 };
43
44 enum TBIE_t {
45 TBIE_OFF = (0x0000), /* Timer A counter interrupt enable */
46 TBIE = 0x0002 /* Timer A counter interrupt enable */
47 };
48
49 enum TBIFG_t {
50 TBIFG_OFF = (0x000), /* Timer A counter interrupt flag */
51 TBIFG = (0x0001) /* Timer A counter interrupt flag */
52 };
53
54 enum MC_t {
55 MC_0 = (0*0x10u), /*! Stop Mode */
56 MC_1 = (1*0x10u), /*! Up Mode */
57 MC_2 = (2*0x10u), /*! Continuous Mode */
58 MC_3 = 3*0x10u /*! Up/Down Mode */
59 };
60
61 enum ID_t {
62 ID_0 = (0*0x40u), /*! Divider - /1 */
63 ID_1 = (1*0x40u), /*! Divider - /2 */
64 ID_2 = (2*0x40u), /*! Divider - /4 */
65 ID_3 = 3*0x40u /*! Divider - /8 */
66 };
67
68 enum CM_t {
69 CM_0 = (0*0x4000u), /*! No Capture */
70 CM_1 = (1*0x4000u), /*! Rising Edge */
71 CM_2 = (2*0x4000u), /*! Falling Edge */
72 CM_3 = 3*0x4000u /*! Both Edges */
73 };
74
75 enum CCIS_t {
76 CCIS_0 = (0*0x1000u), /*! CCIxA */
77 CCIS_1 = (1*0x1000u), /*! CCIxB */
78 CCIS_2 = (2*0x1000u), /*! GND */
79 CCIS_3 = 3*0x1000u /*! Vcc */
80 };
81
82 enum SCS_t {
83 SCS_OFF = (0x0000), /* Asynchronous Capture */
84 SCS = 0x0800 /* Sychronous Capture */
85 };
86
87 enum CLLD_t {
88 CLLD_0 = (0*0x1000u), /* TBCLx loads on write to TBCCRx */
89 CLLD_1 = (1*0x1000u), /* TBCLx loads when TBR counts to 0 */
90 CLLD_2 = (2*0x1000u), /* TBCLx loads when TBR counts to 0 (up or continuous mode) */
91 CLLD_3 = 3*0x1000u /* TBCLx loads when TBR counts to TBCLx */
92 };
93
94 enum SCCI_t {
95 SCCI_OFF = (0x0000), /* Latched capture signal (read) */
96 SCCI = 0x0400 /* Latched capture signal (read) */
97 };
98
99 enum CAP_t {
100 CAP_OFF = (0x0000), /* Compare mode */
101 CAP = 0x0100 /* Capture mode */
102 };
103
104 enum CCIE_t {
105 CCIE_OFF = (0x0000), /* Capture/compare interrupt disable */
106 CCIE = (0x0010) /* Capture/compare interrupt enable */
107 };
108
109 enum CCI_t {
110 CCI_OFF = (0x0008), /* Capture input signal (read) */
111 CCI = (0x0008) /* Capture input signal (read) */
112 };
113
114 enum OUT_t {
115 OUT_OFF = (0x0000), /* PWM Output signal if output mode 0 */
116 OUT = (0x0004) /* PWM Output signal if output mode 0 */
117 };
118
119 enum COV_t {
120 COV_OFF = (0x0000), /* Capture/compare overflow flag */
121 COV = (0x0002) /* Capture/compare overflow flag */
122 };
123
124 enum CCIFG_t {
125 CCIFG_OFF = (0x0000), /* Capture/compare interrupt flag */
126 CCIFG = (0x0001) /* Capture/compare interrupt flag */
127 };
128
129 enum OUTMOD_t {
130 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
131 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
132 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
133 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
134 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
135 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
136 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
137 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
138 };
139
140 /*!
141 * ======== TBCTL_t ========
142 * Timer_B Control Register
143 *
144 * @see #TBCTL_t
145 */
146 struct TBCTL_t {
147 TBCLGRP_t TBCLGRP; /*! TBCLx group
148 * 00 Each TBCLx latch loads independently
149 * 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)
150 * TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)
151 * TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)
152 * TBCL0 independent
153 * 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)
154 * TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
155 * TBCL0 independent
156 * 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6
157 * (TBCCR1 CLLDx bits control the update) */
158 CNTL_t CNTL; /*! Counter Length
159 * 00 16-bit, TBR(max) = 0FFFFh
160 * 01 12-bit, TBR(max) = 0FFFh
161 * 10 10-bit, TBR(max) = 03FFh
162 * 11 8-bit, TBR(max) = 0FFh */
163 TBSSEL_t TBSSEL; /*! Timer_B clock source select.
164 * 00 TBCLK
165 * 01 ACLK
166 * 10 SMCLK
167 * 11 Inverted TBCLK */
168 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
169 * 00 /1
170 * 01 /2
171 * 10 /4
172 * 11 /8 */
173 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_B is not in use conserves
174 * power.
175 * 00 Stop mode: the timer is halted
176 * 01 Up mode: the timer counts up to TBCL0
177 * 10 Continuous mode: the timer counts up to the value set by CNTLx
178 * 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h */
179 TBCLR_t TBCLR; /*! Timer_B clear. Setting this bit resets TBR, the clock divider, and the count
180 * direction. The TBCLR bit is automatically reset and is always read as zero. */
181 TBIE_t TBIE; /*! Timer_B interrupt enable. This bit enables the TBIFG interrupt request.
182 * 0 Interrupt disabled
183 * 1 Interrupt enabled */
184 TBIFG_t TBIFG; /*! Timer_B interrupt flag.
185 * 0 No interrupt pending
186 * 1 Interrupt pending */
187 }
188
189 /* TBCCTLx */
190 struct TBCCTLx_t {
191 CM_t CM; /*! Capture mode
192 * 00 No capture
193 * 01 Capture on rising edge
194 * 10 Capture on falling edge
195 * 11 Capture on both rising and falling edges */
196 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TBCCRx input signal.
197 * See the device-specific data sheet for specific signal connections.
198 * 00 CCIxA
199 * 01 CCIxB
200 * 10 GND
201 * 11 VCC */
202 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
203 * signal with the timer clock.
204 * 0 Asynchronous capture
205 * 1 Synchronous capture */
206 CLLD_t CLLD; /*! Compare latch load. These bits select the compare latch load event.
207 * 00 TBCLx loads on write to TBCCRx
208 * 01 TBCLx loads when TBR counts to 0
209 * 10 TBCLx loads when TBR counts to 0 (up or continuous mode)
210 * TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode)
211 * 11 TBCLx loads when TBR counts to TBCLx */
212 CAP_t CAP; /*! Capture mode
213 * 0 Compare mode
214 * 1 Capture mode */
215 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx
216 * = EQU0.
217 * 000 OUT bit value
218 * 001 Set
219 * 010 Toggle/reset
220 * 011 Set/reset
221 * 100 Toggle
222 * 101 Reset
223 * 110 Toggle/set
224 * 111 Reset/set */
225 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
226 * the corresponding CCIFG flag.
227 * 0 Interrupt disabled
228 * 1 Interrupt enabled */
229 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
230 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
231 * 0 Output low
232 * 1 Output high */
233 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
234 * be reset with software.
235 * 0 No capture overflow occurred
236 * 1 Capture overflow occurred */
237 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
238 * 0 No interrupt pending
239 * 1 Interrupt pending */
240 }
241
242 instance:
243
244 /*! Timer_B TBCLK */
245 config float TBCLK = 0;
246
247 /*! Timer_B INCLK */
248 config float INCLK = 0;
249 }