1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2008 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     * 
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     * 
    11     * --/COPYRIGHT--*/
    12    /*!
    13     *  ======== IE2 ========
    14     *  MSP430 Interrupt Enable Register 2
    15     */
    16    metaonly module IE2 inherits xdc.platform.IPeripheral {
    17    
    18        /* USCI_B0 transmit interrupt enable */
    19        enum UCB0TXIE_t {
    20            UCB0TXIE_OFF = 0x00,            /*! Interrupt disabled */
    21            UCB0TXIE     = 0x08             /*! Interrupt enabled */
    22        };
    23    
    24        /* USCI_B0 receive interrupt enable */
    25        enum UCB0RXIE_t {
    26            UCB0RXIE_OFF = 0x00,            /*! Interrupt disabled */
    27            UCB0RXIE     = 0x04             /*! Interrupt enabled */
    28        };
    29        
    30        /* USCI_A0 transmit interrupt enable */
    31        enum UCA0TXIE_t {
    32            UCA0TXIE_OFF = 0x00,            /*! Interrupt disabled */
    33            UCA0TXIE     = 0x02             /*! Interrupt enabled */
    34        };
    35        
    36        /* USCI_A0 receive interrupt enable */
    37        enum UCA0RXIE_t {
    38            UCA0RXIE_OFF = 0x00,            /*! Interrupt disabled */
    39            UCA0RXIE     = 0x01             /*! Interrupt enabled */
    40        };
    41        
    42        /* USCI_B0 transmit interrupt flag */
    43        enum UCB0TXIFG_t {
    44            UCB0TXIFG_OFF = 0x00,           /*! No interrupt pending */
    45            UCB0TXIFG     = 0x08            /*! Interrupt pending */
    46        };
    47    
    48        /* USCI_B0 receive interrupt flag */
    49        enum UCB0RXIFG_t {
    50            UCB0RXIFG_OFF = 0x00,           /*! No interrupt pending */
    51            UCB0RXIFG     = 0x04            /*! Interrupt pending */
    52        };
    53    
    54        /* USCI_A0 transmit interrupt flag */
    55        enum UCA0TXIFG_t {
    56            UCA0TXIFG_OFF = 0x00,           /*! No interrupt pending */
    57            UCA0TXIFG     = 0x02            /*! Interrupt pending */
    58        };
    59    
    60        /* USCI_A0 receive interrupt flag */
    61        enum UCA0RXIFG_t {
    62            UCA0RXIFG_OFF = 0x00,           /*! No interrupt pending */
    63            UCA0RXIFG     = 0x01            /*! Interrupt pending */
    64        };
    65        
    66        /*! IE2, Interrupt Enable Register 2 */
    67        struct IE2_t {
    68            UCB0TXIE_t  UCB0TXIE;           /*! USCI_B0 transmit interrupt enable
    69                                             *  0 Interrupt disabled
    70                                             *  1 Interrupt enabled */
    71            UCB0RXIE_t  UCB0RXIE;           /*! USCI_B0 receive interrupt enable
    72                                             *  0 Interrupt disabled
    73                                             *  1 Interrupt enabled */
    74            UCA0TXIE_t  UCA0TXIE;           /*! USCI_A0 transmit interrupt enable
    75                                             *  0 Interrupt disabled
    76                                             *  1 Interrupt enabled */
    77            UCA0RXIE_t  UCA0RXIE;           /*! USCI_A0 receive interrupt enable
    78                                             *  0 Interrupt disabled
    79                                             *  1 Interrupt enabled */
    80        }
    81    
    82        /*! IFG2, Interrupt Flag Register 2 */
    83        struct IFG2_t {
    84            UCB0TXIFG_t  UCB0TXIFG;         /*! USCI_B0 transmit interrupt flag
    85                                             *  0 No interrupt pending
    86                                             *  1 Interrupt pending */
    87            UCB0RXIFG_t  UCB0RXIFG;         /*! USCI_B0 receive interrupt flag
    88                                             *  0 No interrupt pending
    89                                             *  1 Interrupt pending */
    90            UCA0TXIFG_t  UCA0TXIFG;         /*! USCI_A0 transmit interrupt flag
    91                                             *  0 No interrupt pending
    92                                             *  1 Interrupt pending */
    93            UCA0RXIFG_t  UCA0RXIFG;         /*! USCI_A0 receive interrupt flag
    94                                             *  0 No interrupt pending
    95                                             *  1 Interrupt pending */
    96        }
    97        
    98        /*!
    99        *  ======== ForceSetDefaultRegister_t ========
   100        *  Force Set Default Register
   101        *
   102        *  Type to store if each register needs to be forced initialized
   103        *  even if the register is in default state.
   104        *
   105        *  @see #ForceSetDefaultRegister_t
   106        */
   107        struct ForceSetDefaultRegister_t {
   108            String     register;
   109            Bool       regForceSet;
   110        }
   111        
   112    instance:
   113        /*! IE2, Interrupt Enable Register 2 */
   114        config IE2_t IE2 = {
   115            UCB0TXIE    : UCB0TXIE_OFF,
   116            UCB0RXIE    : UCB0RXIE_OFF,
   117            UCA0TXIE    : UCA0TXIE_OFF,
   118            UCA0RXIE    : UCA0RXIE_OFF,
   119        };
   120        
   121        /*! IFG2, Interrupt Flag Register 2 */
   122        config IFG2_t IFG2 = {
   123            UCB0TXIFG   : UCB0TXIFG_OFF,
   124            UCB0RXIFG   : UCB0RXIFG_OFF,
   125            UCA0TXIFG   : UCA0TXIFG_OFF,
   126            UCA0RXIFG   : UCA0RXIFG_OFF,
   127        };
   128        
   129       /*!
   130        *  ======== getUCB0TXIE ========
   131        *  Gets UCB0TXIE bit
   132        *
   133        *  @see #getUCB0TXIE
   134        */
   135        Bool    getUCB0TXIE();
   136        
   137       /*!
   138        *  ======== setUCB0TXIE ========
   139        *  Sets UCB0TXIE bit
   140        *
   141        *  @see #setUCB0TXIE
   142        */
   143        Bool    setUCB0TXIE(Bool set);
   144        
   145       /*!
   146        *  ======== getUCB0RXIE ========
   147        *  Gets UCB0RXIE bit
   148        *
   149        *  @see #getUCB0RXIE
   150        */
   151        Bool    getUCB0RXIE();
   152        
   153       /*!
   154        *  ======== setUCB0RXIE ========
   155        *  Sets UCB0RXIE bit
   156        *
   157        *  @see #setUCB0RXIE
   158        */
   159        Bool    setUCB0RXIE(Bool set);
   160        
   161       /*!
   162        *  ======== getUCA0TXIE ========
   163        *  Gets UCA0TXIE bit
   164        *
   165        *  @see #getUCA0TXIE
   166        */
   167        Bool    getUCA0TXIE();
   168        
   169       /*!
   170        *  ======== setUCA0TXIE ========
   171        *  Sets UCA0TXIE bit
   172        *
   173        *  @see #setUCA0TXIE
   174        */
   175        Bool    setUCA0TXIE(Bool set);
   176        
   177       /*!
   178        *  ======== getUCA0RXIE ========
   179        *  Gets UCA0RXIE bit
   180        *
   181        *  @see #getUCA0RXIE
   182        */
   183        Bool    getUCA0RXIE();
   184        
   185       /*!
   186        *  ======== setUCA0RXIE ========
   187        *  Sets UCA0RXIE bit
   188        *
   189        *  @see #setUCA0RXIE
   190        */
   191        Bool    setUCA0RXIE(Bool set);
   192    
   193        /*!
   194         *  ======== forceSetDefaultRegister ========
   195         *  Determine if each Register needs to be forced set or not
   196         */
   197        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   198        [
   199            { register : "IE2" , regForceSet : false },
   200            { register : "IFG2" , regForceSet : false },
   201        ];
   202    }