1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.communication.USI as USI;
13 import ti.catalog.msp430.peripherals.adc.ADC10 as ADC10;
14
15 /*!
16 * ======== GPIO for MSP430G2x31 ========
17 * MSP430 General Purpose Input Output Ports
18 */
19 metaonly module GPIO_MSP430G2x31 inherits IGPIO {
20 /*!
21 * ======== create ========
22 * Create an instance of this peripheral.
23 */
24 create(USI.Instance usi, ADC10.Instance adc10);
25
26 instance:
27 /*! @_nodoc */
28 config USI.Instance usi;
29
30 /*! @_nodoc */
31 config ADC10.Instance adc10;
32
33 /*! Define an array to describe all device pins. The 1st dimension
34 * denotes the port, the second the pin on that port. On an
35 * MSP430G2x31 device, there are 8 + 2 = 10 pins total.
36 */
37
38 39
40 41
42 config DevicePin_t devicePins[2][8];
43
44 /*! Implementation of Device Pin Functional Configuration */
45 override config DevicePinFunctionSetting_t devicePinSetting[2][8];
46
47 /*! Determine if each Register needs to be forced set or not */
48 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
49 [
50 { register : "P1OUT" , regForceSet : true },
51 { register : "P1SEL" , regForceSet : false },
52 { register : "P1DIR" , regForceSet : false },
53 { register : "P1REN" , regForceSet : false },
54 { register : "P1IES" , regForceSet : true },
55 { register : "P1IFG" , regForceSet : true },
56 { register : "P1IE" , regForceSet : false },
57 { register : "P2OUT" , regForceSet : true },
58 { register : "P2SEL" , regForceSet : false },
59 { register : "P2DIR" , regForceSet : false },
60 { register : "P2REN" , regForceSet : false },
61 { register : "P2IES" , regForceSet : true },
62 { register : "P2IFG" , regForceSet : true },
63 { register : "P2IE" , regForceSet : false }
64 ];
65
66 67 68 69 70 71
72
73 /*! Port 1 Output Register */
74 config GpioBits8PxOut_t P1OUT = {
75 Bit0 : BIT0_OFF,
76 Bit1 : BIT1_OFF,
77 Bit2 : BIT2_OFF,
78 Bit3 : BIT3_OFF,
79 Bit4 : BIT4_OFF,
80 Bit5 : BIT5_OFF,
81 Bit6 : BIT6_OFF,
82 Bit7 : BIT7_OFF
83 };
84
85 /*! Port 1 Port Select Register */
86 config GpioBits8PxSel_t P1SEL = {
87 Bit0 : BIT0_OFF,
88 Bit1 : BIT1_OFF,
89 Bit2 : BIT2_OFF,
90 Bit3 : BIT3_OFF,
91 Bit4 : BIT4_OFF,
92 Bit5 : BIT5_OFF,
93 Bit6 : BIT6_OFF,
94 Bit7 : BIT7_OFF
95 };
96
97 /*! Port 1 Direction Register */
98 config GpioBits8PxDir_t P1DIR = {
99 Bit0 : BIT0_OFF,
100 Bit1 : BIT1_OFF,
101 Bit2 : BIT2_OFF,
102 Bit3 : BIT3_OFF,
103 Bit4 : BIT4_OFF,
104 Bit5 : BIT5_OFF,
105 Bit6 : BIT6_OFF,
106 Bit7 : BIT7_OFF
107 };
108
109 /*! Port 1 Resistor Enable Register */
110 config GpioBits8PxRen_t P1REN = {
111 Bit0 : BIT0_OFF,
112 Bit1 : BIT1_OFF,
113 Bit2 : BIT2_OFF,
114 Bit3 : BIT3_OFF,
115 Bit4 : BIT4_OFF,
116 Bit5 : BIT5_OFF,
117 Bit6 : BIT6_OFF,
118 Bit7 : BIT7_OFF
119 };
120
121 /*! Port 1 Interrupt Edge Select Register */
122 config GpioBits8PxIes_t P1IES = {
123 Bit0 : BIT0_OFF,
124 Bit1 : BIT1_OFF,
125 Bit2 : BIT2_OFF,
126 Bit3 : BIT3_OFF,
127 Bit4 : BIT4_OFF,
128 Bit5 : BIT5_OFF,
129 Bit6 : BIT6_OFF,
130 Bit7 : BIT7_OFF
131 };
132
133 /*! Port 1 Interrupt Flag Register */
134 config GpioBits8PxIfg_t P1IFG = {
135 Bit0 : BIT0_OFF,
136 Bit1 : BIT1_OFF,
137 Bit2 : BIT2_OFF,
138 Bit3 : BIT3_OFF,
139 Bit4 : BIT4_OFF,
140 Bit5 : BIT5_OFF,
141 Bit6 : BIT6_OFF,
142 Bit7 : BIT7_OFF
143 };
144
145 /*! Port 1 Interrupt Enable Register */
146 config GpioBits8PxIe_t P1IE = {
147 Bit0 : BIT0_OFF,
148 Bit1 : BIT1_OFF,
149 Bit2 : BIT2_OFF,
150 Bit3 : BIT3_OFF,
151 Bit4 : BIT4_OFF,
152 Bit5 : BIT5_OFF,
153 Bit6 : BIT6_OFF,
154 Bit7 : BIT7_OFF
155 };
156
157 /*! Port 2 Output Register */
158 config GpioBits8PxOut_t P2OUT = {
159 Bit0 : BIT0_OFF,
160 Bit1 : BIT1_OFF,
161 Bit2 : BIT2_OFF,
162 Bit3 : BIT3_OFF,
163 Bit4 : BIT4_OFF,
164 Bit5 : BIT5_OFF,
165 Bit6 : BIT6_OFF,
166 Bit7 : BIT7_OFF
167 };
168
169 /*! Port 2 Port Select Register */
170 config GpioBits8PxSel_t P2SEL = {
171 Bit0 : BIT0_OFF,
172 Bit1 : BIT1_OFF,
173 Bit2 : BIT2_OFF,
174 Bit3 : BIT3_OFF,
175 Bit4 : BIT4_OFF,
176 Bit5 : BIT5_OFF,
177 Bit6 : BIT6,
178 Bit7 : BIT7
179 };
180
181 /*! Port 2 Direction Register */
182 config GpioBits8PxDir_t P2DIR = {
183 Bit0 : BIT0_OFF,
184 Bit1 : BIT1_OFF,
185 Bit2 : BIT2_OFF,
186 Bit3 : BIT3_OFF,
187 Bit4 : BIT4_OFF,
188 Bit5 : BIT5_OFF,
189 Bit6 : BIT6_OFF,
190 Bit7 : BIT7_OFF
191 };
192
193 /*! Port 2 Resistor Enable Register */
194 config GpioBits8PxRen_t P2REN = {
195 Bit0 : BIT0_OFF,
196 Bit1 : BIT1_OFF,
197 Bit2 : BIT2_OFF,
198 Bit3 : BIT3_OFF,
199 Bit4 : BIT4_OFF,
200 Bit5 : BIT5_OFF,
201 Bit6 : BIT6_OFF,
202 Bit7 : BIT7_OFF
203 };
204
205 /*! Port 2 Interrupt Edge Select Register */
206 config GpioBits8PxIes_t P2IES = {
207 Bit0 : BIT0_OFF,
208 Bit1 : BIT1_OFF,
209 Bit2 : BIT2_OFF,
210 Bit3 : BIT3_OFF,
211 Bit4 : BIT4_OFF,
212 Bit5 : BIT5_OFF,
213 Bit6 : BIT6_OFF,
214 Bit7 : BIT7_OFF
215 };
216
217 /*! Port 2 Interrupt Flag Register */
218 config GpioBits8PxIfg_t P2IFG = {
219 Bit0 : BIT0_OFF,
220 Bit1 : BIT1_OFF,
221 Bit2 : BIT2_OFF,
222 Bit3 : BIT3_OFF,
223 Bit4 : BIT4_OFF,
224 Bit5 : BIT5_OFF,
225 Bit6 : BIT6_OFF,
226 Bit7 : BIT7_OFF
227 };
228
229 /*! Port 2 Interrupt Enable Register */
230 config GpioBits8PxIe_t P2IE = {
231 Bit0 : BIT0_OFF,
232 Bit1 : BIT1_OFF,
233 Bit2 : BIT2_OFF,
234 Bit3 : BIT3_OFF,
235 Bit4 : BIT4_OFF,
236 Bit5 : BIT5_OFF,
237 Bit6 : BIT6_OFF,
238 Bit7 : BIT7_OFF
239 };
240 }