1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Universal Serial Communication Interface A0 SPI 2xx
16 */
17 metaonly module USCI_A0_SPI_2xx inherits IUSCI_A0_SPI {
18 19 20
21 create(IClock.Instance clock);
22
23
24
25 instance:
26 /*! @_nodoc */
27 config IClock.Instance clock;
28
29 /*! Determine if each Register needs to be forced set or not */
30 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
31 [
32 { register : "UCA0CTL0" , regForceSet : false },
33 { register : "UCA0CTL1" , regForceSet : false },
34 { register : "UCA0BR0" , regForceSet : false },
35 { register : "UCA0BR1" , regForceSet : false },
36 { register : "UCA0STAT" , regForceSet : false },
37 { register : "UCA0RXBUF" , regForceSet : false },
38 { register : "UCA0TXBUF" , regForceSet : false }
39 ];
40 }