1 /*
2 * Copyright (c) 2011 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Boot.xdc ========
15 *
16 */
17
18 package ti.catalog.arm.cortexm3.concertoInit;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Concerto M3 Boot Support.
25 *
26 * The Boot module supports boot initialization for the Concerto M3 core.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
45 metaonlyenum FractMult {
46 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
47 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
48 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
49 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
50 }
51
52 /*! System Clock Divider (SYSDIVSEL) value */
53 metaonlyenum SysDiv {
54 Div_1 = 0x0, /*! Divide by 1 */
55 Div_2 = 0x1, /*! Divide by 2 */
56 Div_4 = 0x2, /*! Divide by 4 */
57 Div_8 = 0x3 /*! Divide by 8 */
58 };
59
60 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
61 metaonlyenum M3Div {
62 M3Div_1 = 0x0, /*! Divide by 1 */
63 M3Div_2 = 0x1, /*! Divide by 2 */
64 M3Div_4 = 0x2 /*! Divide by 4 */
65 };
66
67 metaonlystruct ModuleView {
68 Bool configureClocks;
69 UInt OSCCLK;
70 UInt SPLLIMULT;
71 String SPLLFMULT;
72 String SYSDIVSEL;
73 String M3SSDIVSEL;
74 Bool bootC28;
75 UInt bootAddressC28;
76 }
77
78 @Facet
79 metaonlyconfig ViewInfo.Instance rovViewInfo =
80 ViewInfo.create({
81 viewMap: [
82 [
83 'Module',
84 {
85 type: ViewInfo.MODULE,
86 viewInitFxn: 'viewInitModule',
87 structName: 'ModuleView'
88 }
89 ],
90 ]
91 });
92
93 /*!
94 * Clock configuration flag, default is false.
95 *
96 * Set to true to configure the PLL and system and M3 subsystem clock
97 * dividers.
98 */
99 config Bool configureClocks = false;
100
101 /*!
102 * OSCCLK input frequency to PLL, in MHz. Default is 20 MHz.
103 *
104 * This is the frequency of the oscillator clock (OSCCLK) input to the
105 * PLL.
106 */
107 metaonlyconfig UInt OSCCLK = 20;
108
109 /*! System PLL Integer Multiplier (SPLLIMULT) value */
110 metaonlyconfig UInt SPLLIMULT = 1;
111
112 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
113 metaonlyconfig FractMult SPLLFMULT = Fract_0;
114
115 /*! System Clock Divider (SYSDIVSEL) value */
116 metaonlyconfig SysDiv SYSDIVSEL = Div_8;
117
118 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
119 metaonlyconfig M3Div M3SSDIVSEL = M3Div_4;
120
121 /*!
122 * Function to be called when Limp mode is detected.
123 *
124 * This function is called when the Boot module is about to configure
125 * the PLL, but finds the device operating in Limp mode (i.e., the mode
126 * when a missing OSCCLK input has been detected).
127 *
128 * If this function is not specified by the application, a default
129 * function will be used, which spins in an infinite loop.
130 */
131 metaonlyconfig Fxn limpAbortFunction;
132
133 /*!
134 * Boot from FLASH flag. Default is true.
135 *
136 * Set to true to enable booting the M3 from FLASH.
137 */
138 metaonlyconfig Bool bootFromFlash = true;
139
140 /*!
141 * Initiate booting of the C28 processor. Default is false.
142 *
143 * Set to true to enable the M3 to initiate boot of the C28.
144 *
145 * The address the C28 should boot from is defined by
146 * `{@link #bootAddressC28}`.
147 *
148 * If enabled, this will occur after the optional clock configuration
149 * step, enabled by `{@link #configureClocks}`.
150 */
151 metaonlyconfig Bool bootC28 = false;
152
153 /*!
154 * Address the C28 processor should boot from. Default is 0x13fffe.
155 *
156 * When booting the C28 (see `{@link #bootC28}`), the M3 will send an IPC
157 * command to the C28 processor to start execution at a specific address.
158 * This configuration parameter defines that C28 address.
159 *
160 * The default address of 0x13fffe corresponds to the "BEGIN" address
161 * in the C28 memory map. When the C28 program is configured to boot from
162 * Flash as well (see the ti.catalog.c2800.concertoInit.Boot module),
163 * then a branch to c_int00 instruction is placed at "BEGIN". If a
164 * different address is needed (e.g., if BEGIN is moved, or if a different
165 * customer-provided address is to be used), bootAddressC28 must be changed
166 * accordingly.
167 */
168 metaonlyconfig UInt bootAddressC28 = 0x13fffe;
169
170 /*!
171 * @_nodoc 172 * ======== getFrequency ========
173 * Gets the resulting M3 CPU frequency (in Hz) given the Clock
174 * configuration parameters.
175 *
176 */
177 UInt32 getFrequency();
178
179 /*!
180 * @_nodoc 181 * ======== registerFreqListener ========
182 * Register a module to be notified whenever the frequency changes.
183 *
184 * The registered module must have a function named 'fireFrequencyUpdate'
185 * which takes the new frequency as an argument.
186 */
187 function registerFreqListener();
188
189 internal:
190
191 /* Used to display the computed frequency value in the Grace page. */
192 metaonlyconfig String displayFrequency;
193
194 };
195 /*
196 * @(#) ti.catalog.arm.cortexm3.concertoInit; 1, 0, 0,3; 7-20-2011 07:06:56; /db/ztree/library/trees/platform/platform-m25x/src/
197 */
198