1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2008 Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * ======== Flash_2xx ========
16 * MSP430F2xx Family Flash Module
17 */
18 metaonly module Flash_2xx inherits IFlash
19 {
20 /* FCTL1 Register */
21 struct FCTL1_t {
22 FWKEY_t FWKEY; /*! FCTLx password Always read as 096h. Must be written as 0A5h or a PUC
23 * will be generated. */
24 BLKWRT_t BLKWRT; /*! Block write mode */
25 WRT_t WRT; /*! Write */
26 EEIEX_t EEIEX; /*! Enable Emergency Interrupt Exit */
27 EEI_t EEI; /*! Enable Erase Interrupts */
28 MERAS_t MERAS; /*! Mass erase */
29 ERASE_t ERASE; /*! Erase */
30 }
31
32 /* FCTL2 Register */
33 struct FCTL2_t {
34 FWKEY_t FWKEY; /*! FCTLx password Always read as 096h. Must be written as 0A5h or a PUC
35 * will be generated. */
36 FSSEL_t FSSEL; /*! Flash controller clock source select
37 * 00 ACLK
38 * 01 MCLK
39 * 10 SMCLK
40 * 11 SMCLK */
41 FN5_t FN5; /*! Flash Controller Clock Divider Bit 5 */
42 FN4_t FN4; /*! Flash Controller Clock Divider Bit 4 */
43 FN3_t FN3; /*! Flash Controller Clock Divider Bit 3 */
44 FN2_t FN2; /*! Flash Controller Clock Divider Bit 2 */
45 FN1_t FN1; /*! Flash Controller Clock Divider Bit 1 */
46 FN0_t FN0; /*! Flash Controller Clock Divider Bit 0 */
47 }
48
49 /* FCTL3 Register */
50 struct FCTL3_t {
51 FWKEY_t FWKEY; /*! FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC
52 * will be generated. */
53 FAIL_t FAIL; /*! FAIL Bit 7 Operation failure. This bit is set if the fFTG clock source fails, or a flash
54 * operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset
55 * with software.
56 * 0 No failure
57 * 1 Failure */
58 LOCKA_t LOCKA; /*! SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has
59 * no effect.
60 * 0 Segment A unlocked and all information memory is erased during a
61 * mass erase.
62 * 1 Segment A locked and all information memory is protected from erasure
63 * during a mass erase. */
64 EMEX_t EMEX; /*! Emergency exit
65 * 0 No emergency exit
66 * 1 Emergency exit */
67 LOCK_t LOCK; /*! Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit
68 * can be set anytime during a byte/word write or erase operation and the
69 * operation will complete normally. In the block write mode if the LOCK bit is set
70 * while BLKWRT=WAIT=1, then BLKWRT and WAIT are reset and the mode
71 * ends normally.
72 * 0 Unlocked
73 * 1 Locked */
74 WAIT_t WAIT; /*! Wait. Indicates the flash memory is being written to.
75 * 0 The flash memory is not ready for the next byte/word write
76 * 1 The flash memory is ready for the next byte/word write */
77 ACCVIFG_t ACCVIFG; /*! Access violation interrupt flag
78 * 0 No interrupt pending
79 * 1 Interrupt pending */
80 KEYV_t KEYV; /*! Flash security key violation. This bit indicates an incorrect FCTLx password
81 * was written to any flash control register and generates a PUC when set. KEYV
82 * must be reset with software.
83 * 0 FCTLx password was written correctly
84 * 1 FCTLx password was written incorrectly */
85 BUSY_t BUSY; /*! Busy. This bit indicates the status of the flash timing generator.
86 * 0 Not Busy
87 * 1 Busy */
88 }
89
90 /*
91 * ======== create ========
92 */
93 create(IClock.Instance clock);
94
95 instance:
96 /*! Flash Memory Control Register 1 */
97 config FCTL1_t FCTL1 = {
98 FWKEY : FWKEY,
99 BLKWRT : BLKWRT_OFF,
100 WRT : WRT_OFF,
101 EEIEX : EEIEX_OFF,
102 EEI : EEI_OFF,
103 MERAS : MERAS_OFF,
104 ERASE : ERASE_OFF
105 };
106
107 /*! Flash Memory Control Register 2 */
108 config FCTL2_t FCTL2 = {
109 FWKEY : FWKEY,
110 FSSEL : FSSEL_1,
111 FN5 : FN5_OFF,
112 FN4 : FN4_OFF,
113 FN3 : FN3_OFF,
114 FN2 : FN2_OFF,
115 FN1 : FN1,
116 FN0 : FN0_OFF
117 };
118
119 /*! Flash Memory Control Register 3 */
120 config FCTL3_t FCTL3 = {
121 FAIL : FAIL_OFF,
122 LOCKA : LOCKA_OFF,
123 EMEX : EMEX_OFF,
124 LOCK : LOCK,
125 WAIT : WAIT,
126 ACCVIFG : ACCVIFG_OFF,
127 KEYV : KEYV_OFF,
128 BUSY : BUSY_OFF
129 };
130
131 /*! Determine if each Register needs to be forced set or not */
132 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] = [
133 { register : "FCTL1" , regForceSet : false },
134 { register : "FCTL2" , regForceSet : false },
135 { register : "FCTL3" , regForceSet : false }
136 ];
137
138 config IClock.Instance clock;
139 }