1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== ADC12 ========
14 * MSP430 12-bit Analog to Digital Converter
15 */
16 metaonly module ADC12 inherits IADC {
17
18
19 /*! SHT1 Bits */
20 enum ADC12SHT1_t {
21 SHT1_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
22 SHT1_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
23 SHT1_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
24 SHT1_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
25 SHT1_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
26 SHT1_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
27 SHT1_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
28 SHT1_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
29 SHT1_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
30 SHT1_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
31 SHT1_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
32 SHT1_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
33 SHT1_12 = (12*0x1000u), /*! 1024 ADC12CLK cycles */
34 SHT1_13 = (13*0x1000u), /*! 1024 ADC12CLK cycles */
35 SHT1_14 = (14*0x1000u), /*! 1024 ADC12CLK cycles */
36 SHT1_15 = 15*0x1000u /*! 1024 ADC12CLK cycles */
37 };
38
39 /*! SHT0 Bits */
40 enum ADC12SHT0_t {
41 SHT0_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
42 SHT0_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
43 SHT0_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
44 SHT0_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
45 SHT0_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
46 SHT0_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
47 SHT0_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
48 SHT0_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
49 SHT0_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
50 SHT0_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
51 SHT0_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
52 SHT0_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
53 SHT0_12 = (12*0x1000u), /*! 1024 ADC12CLK cycles */
54 SHT0_13 = (13*0x1000u), /*! 1024 ADC12CLK cycles */
55 SHT0_14 = (14*0x1000u), /*! 1024 ADC12CLK cycles */
56 SHT0_15 = 15*0x1000u /*! 1024 ADC12CLK cycles */
57 };
58
59 /*! MSC Bit */
60 enum MSC_t {
61 MSC_OFF = 0x000, /*! The sampling timer requires a rising edge of the SHI
62 * signal to trigger each sample-and-conversion */
63 MSC = 0x080 /*! The first rising edge of the SHI signal triggers
64 * the sampling timer, but further sample-and-conversions
65 * are performed automatically as soon as the prior conversion
66 * is completed */
67 };
68
69 /*! REF2_5V Bit */
70 enum REF2_5V_t {
71 REF2_5V_OFF = 0x000, /*! 1.5V */
72 REF2_5V = 0x040 /*! 2.5V */
73 };
74
75 /*! REFON Bit */
76 enum REFON_t {
77 REFON_OFF = 0x000, /*! Reference off */
78 REFON = 0x020 /*! Reference on */
79 };
80
81 /*! ADC12ON Bit */
82 enum ADC12ON_t {
83 ADC12ON_OFF = 0x000, /*! ADC12 off */
84 ADC12ON = 0x010 /*! ADC12 on */
85 };
86
87 /*! ADC12OVIE Bit */
88 enum ADC12OVIE_t {
89 ADC12OVIE_OFF = 0x000, /*! Overflow interrupt disabled */
90 ADC12OVIE = 0x008 /*! Overflow interrupt enabled */
91 };
92
93 /*! ADC12TOVIE Bit */
94 enum ADC12TOVIE_t {
95 ADC12TOVIE_OFF = 0x000, /*! Conversion time overflow interrupt disabled */
96 ADC12TOVIE = 0x004 /*! Conversion time overflow interrupt disabled */
97 };
98
99 /*! ENC Bit */
100 enum ENC_t {
101 ENC_OFF = 0x000, /*! ADC12 disabled */
102 ENC = 0x002 /*! ADC12 enabled */
103 };
104
105 /*! ADC12SC Bit */
106 enum ADC12SC_t {
107 ADC12SC_OFF = 0x000, /*! No sample-and-conversion-start */
108 ADC12SC = 0x001 /*! Start sample-and-conversion */
109 };
110
111 /*! CSTARTADD Bits */
112 enum CSTARTADD_t {
113 CSTARTADD_0 = (0*0x1000u), /*! ADC12MEM0 */
114 CSTARTADD_1 = (1*0x1000u), /*! ADC12MEM1 */
115 CSTARTADD_2 = (2*0x1000u), /*! ADC12MEM2 */
116 CSTARTADD_3 = (3*0x1000u), /*! ADC12MEM3 */
117 CSTARTADD_4 = (4*0x1000u), /*! ADC12MEM4 */
118 CSTARTADD_5 = (5*0x1000u), /*! ADC12MEM5 */
119 CSTARTADD_6 = (6*0x1000u), /*! ADC12MEM6 */
120 CSTARTADD_7 = (7*0x1000u), /*! ADC12MEM7 */
121 CSTARTADD_8 = (8*0x1000u), /*! ADC12MEM8 */
122 CSTARTADD_9 = (9*0x1000u), /*! ADC12MEM9 */
123 CSTARTADD_10 = (10*0x1000u), /*! ADC12MEM10 */
124 CSTARTADD_11 = (11*0x1000u), /*! ADC12MEM11 */
125 CSTARTADD_12 = (12*0x1000u), /*! ADC12MEM12 */
126 CSTARTADD_13 = (13*0x1000u), /*! ADC12MEM13 */
127 CSTARTADD_14 = (14*0x1000u), /*! ADC12MEM14 */
128 CSTARTADD_15 = 15*0x1000u /*! ADC12MEM15 */
129 };
130
131 /*! SHS Bits */
132 enum SHS_t {
133 SHS_0 = (0*0x400u), /*! ADC12SC bit */
134 SHS_1 = (1*0x400u), /*! Timer_A.OUT1 */
135 SHS_2 = (2*0x400u), /*! Timer_B.OUT0 */
136 SHS_3 = 3*0x400u /*! Timer_B.OUT1 */
137 };
138
139 /*! SHP Bits */
140 enum SHP_t {
141 SHP_OFF = 0x0000, /*! SAMPCON signal is sourced from the sample-input signal */
142 SHP = 0x0200 /*! SAMPCON signal is sourced from the sampling timer. */
143 };
144
145 /*! ISSH Bits */
146 enum ISSH_t {
147 ISSH_OFF = 0x0000, /*! The sample-input signal is not inverted */
148 ISSH = 0x0100 /*! The sample-input signal is inverted */
149 };
150
151
152 /*! ADC12DIV Bits */
153 enum ADC12DIV_t {
154 ADC12DIV_0 = (0*0x20u), /*! Divide by 1 */
155 ADC12DIV_1 = (1*0x20u), /*! Divide by 2 */
156 ADC12DIV_2 = (2*0x20u), /*! Divide by 3 */
157 ADC12DIV_3 = (3*0x20u), /*! Divide by 4 */
158 ADC12DIV_4 = (4*0x20u), /*! Divide by 5 */
159 ADC12DIV_5 = (5*0x20u), /*! Divide by 6 */
160 ADC12DIV_6 = (6*0x20u), /*! Divide by 7 */
161 ADC12DIV_7 = 7*0x20u /*! Divide by 8 */
162 };
163
164 /*! ADC12SSEL Bits */
165 enum ADC12SSEL_t {
166 ADC12SSEL_0 = (0*8u), /*! ADC12OSC */
167 ADC12SSEL_1 = (1*8u), /*! ACLK */
168 ADC12SSEL_2 = (2*8u), /*! MCLK */
169 ADC12SSEL_3 = 3*8u /*! SMCLK */
170 };
171
172 /*! CONSEQ Bits */
173 enum CONSEQ_t {
174 CONSEQ_0 = (0*2u), /*! Single channel single conversion */
175 CONSEQ_1 = (1*2u), /*! Sequence of channels */
176 CONSEQ_2 = (2*2u), /*! Repeat single channel */
177 CONSEQ_3 = 3*2u /*! Repeat sequence of channels */
178 };
179
180 /*! ADC12 Busy Bit */
181 enum ADC12BUSY_t {
182 ADC12BUSY_OFF = 0x0000,
183 ADC12BUSY = 0x0001
184 };
185
186 /*! EOS Bit */
187 enum EOS_t {
188 EOS_OFF = 0x0000, /*! Not end of sequence */
189 EOS = 0x0080 /*! End of sequence */
190 };
191
192 /*! SREF Bits */
193 enum SREF_t {
194 SREF_0 = (0*0x10u), /*! VR+ = AVcc and VR-- = AVss */
195 SREF_1 = (1*0x10u), /*! VR+ = VREF+ and VR-- = AVss */
196 SREF_2 = (2*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
197 SREF_3 = (3*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
198 SREF_4 = (4*0x10u), /*! VR+ = AVcc and VR-- = VREF--/ VeREF-- */
199 SREF_5 = (5*0x10u), /*! VR+ = VREF+ and VR-- = VREF--/ VeREF-- */
200 SREF_6 = (6*0x10u), /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
201 SREF_7 = 7*0x10u /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
202 };
203
204 /*! ADC12 Interrupt Enable Bit 15 */
205 enum ADC12IE15_t {
206 ADC12IE15_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG15 bit */
207 ADC12IE15 = 0x8000 /*! Enable the interrupt request for the ADC12IFG15 bit */
208 };
209
210 /*! ADC12 Interrupt Enable Bit 14 */
211 enum ADC12IE14_t {
212 ADC12IE14_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG14 bit */
213 ADC12IE14 = 0x4000 /*! Enable the interrupt request for the ADC12IFG14 bit */
214 };
215
216 /*! ADC12 Interrupt Enable Bit 13 */
217 enum ADC12IE13_t {
218 ADC12IE13_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG13 bit */
219 ADC12IE13 = 0x2000 /*! Enable the interrupt request for the ADC12IFG13 bit */
220 };
221
222 /*! ADC12 Interrupt Enable Bit 12 */
223 enum ADC12IE12_t {
224 ADC12IE12_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG12 bit */
225 ADC12IE12 = 0x1000 /*! Enable the interrupt request for the ADC12IFG12 bit */
226 };
227
228 /*! ADC12 Interrupt Enable Bit 11 */
229 enum ADC12IE11_t {
230 ADC12IE11_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG11 bit */
231 ADC12IE11 = 0x0800 /*! Enable the interrupt request for the ADC12IFG11 bit */
232 };
233
234 /*! ADC12 Interrupt Enable Bit 10 */
235 enum ADC12IE10_t {
236 ADC12IE10_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG10 bit */
237 ADC12IE10 = 0x0400 /*! Enable the interrupt request for the ADC12IFG10 bit */
238 };
239
240 /*! ADC12 Interrupt Enable Bit 9 */
241 enum ADC12IE9_t {
242 ADC12IE9_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG9 bit */
243 ADC12IE9 = 0x0200 /*! Enable the interrupt request for the ADC12IFG9 bit */
244 };
245
246 /*! ADC12 Interrupt Enable Bit 8 */
247 enum ADC12IE8_t {
248 ADC12IE8_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG8 bit */
249 ADC12IE8 = 0x0100 /*! Enable the interrupt request for the ADC12IFG8 bit */
250 };
251
252 /*! ADC12 Interrupt Enable Bit 7 */
253 enum ADC12IE7_t {
254 ADC12IE7_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG7 bit */
255 ADC12IE7 = 0x0080 /*! Enable the interrupt request for the ADC12IFG7 bit */
256 };
257
258 /*! ADC12 Interrupt Enable Bit 6 */
259 enum ADC12IE6_t {
260 ADC12IE6_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG6 bit */
261 ADC12IE6 = 0x0040 /*! Enable the interrupt request for the ADC12IFG6 bit */
262 };
263
264 /*! ADC12 Interrupt Enable Bit 5 */
265 enum ADC12IE5_t {
266 ADC12IE5_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG5 bit */
267 ADC12IE5 = 0x0020 /*! Enable the interrupt request for the ADC12IFG5 bit */
268 };
269
270 /*! ADC12 Interrupt Enable Bit 4 */
271 enum ADC12IE4_t {
272 ADC12IE4_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG4 bit */
273 ADC12IE4 = 0x0010 /*! Enable the interrupt request for the ADC12IFG4 bit */
274 };
275
276 /*! ADC12 Interrupt Enable Bit 3 */
277 enum ADC12IE3_t {
278 ADC12IE3_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG3 bit */
279 ADC12IE3 = 0x0008 /*! Enable the interrupt request for the ADC12IFG3 bit */
280 };
281
282 /*! ADC12 Interrupt Enable Bit 2 */
283 enum ADC12IE2_t {
284 ADC12IE2_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG2 bit */
285 ADC12IE2 = 0x0004 /*! Enable the interrupt request for the ADC12IFG2 bit */
286 };
287
288 /*! ADC12 Interrupt Enable Bit 1 */
289 enum ADC12IE1_t {
290 ADC12IE1_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG1 bit */
291 ADC12IE1 = 0x0002 /*! Enable the interrupt request for the ADC12IFG1 bit */
292 };
293
294 /*! ADC12 Interrupt Enable Bit 0 */
295 enum ADC12IE0_t {
296 ADC12IE0_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG0 bit */
297 ADC12IE0 = 0x0001 /*! Enable the interrupt request for the ADC12IFG0 bit */
298 };
299
300 /*! INCH Bits */
301 enum INCH_t {
302 INCH_0 = (0), /*! A0 */
303 INCH_1 = (1), /*! A1 */
304 INCH_2 = (2), /*! A2 */
305 INCH_3 = (3), /*! A3 */
306 INCH_4 = (4), /*! A4 */
307 INCH_5 = (5), /*! A5 */
308 INCH_6 = (6), /*! A6 */
309 INCH_7 = (7), /*! A7 */
310 INCH_8 = (8), /*! VeREF+ */
311 INCH_9 = (9), /*! VREF--/VeREF- */
312 INCH_10 = (10), /*! Temperature diode */
313 INCH_11 = (11), /*! (AVcc - AVss) / 2 */
314 INCH_12 = (12), /*! GND */
315 INCH_13 = (13), /*! GND */
316 INCH_14 = (14), /*! GND */
317 INCH_15 = 15 /*! GND */
318 };
319
320
321 /*! ADC12IV Definitions */
322 enum ADC12IV_t {
323 ADC12IV_NONE = (0x0000), /*! No Interrupt pending */
324 ADC12IV_ADC12OVIFG = (0x0002), /*! ADC12OVIFG */
325 ADC12IV_ADC12TOVIFG = (0x0004), /*! ADC12TOVIFG */
326 ADC12IV_ADC12IFG0 = (0x0006), /*! ADC12IFG0 */
327 ADC12IV_ADC12IFG1 = (0x0008), /*! ADC12IFG1 */
328 ADC12IV_ADC12IFG2 = (0x000A), /*! ADC12IFG2 */
329 ADC12IV_ADC12IFG3 = (0x000C), /*! ADC12IFG3 */
330 ADC12IV_ADC12IFG4 = (0x000E), /*! ADC12IFG4 */
331 ADC12IV_ADC12IFG5 = (0x0010), /*! ADC12IFG5 */
332 ADC12IV_ADC12IFG6 = (0x0012), /*! ADC12IFG6 */
333 ADC12IV_ADC12IFG7 = (0x0014), /*! ADC12IFG7 */
334 ADC12IV_ADC12IFG8 = (0x0016), /*! ADC12IFG8 */
335 ADC12IV_ADC12IFG9 = (0x0018), /*! ADC12IFG9 */
336 ADC12IV_ADC12IFG10 = (0x001A), /*! ADC12IFG10 */
337 ADC12IV_ADC12IFG11 = (0x001C), /*! ADC12IFG11 */
338 ADC12IV_ADC12IFG12 = (0x001E), /*! ADC12IFG12 */
339 ADC12IV_ADC12IFG13 = (0x0020), /*! ADC12IFG13 */
340 ADC12IV_ADC12IFG14 = (0x0022), /*! ADC12IFG14 */
341 ADC12IV_ADC12IFG15 = 0x0024 /*! ADC12IFG15 */
342 };
343
344 /*! ADC12 Control Register 0 */
345 struct ADC12CTL0_t {
346 ADC12SHT1_t ADC12SHT1; /*! Sample-and-hold time. These bits define the number
347 * of ADC12CLK cycles in the sampling period for registers
348 * ADC12MEM8 to ADC12MEM15. */
349 ADC12SHT0_t ADC12SHT0; /*! Sample-and-hold time. These bits define the number
350 * of ADC12CLK cycles in the sampling period for registers
351 * ADC12MEM0 to ADC12MEM7. */
352 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence
353 * or repeated modes.
354 * 0 The sampling timer requires a rising edge of the SHI signal
355 * to trigger each sample-and-conversion.
356 * 1 The first rising edge of the SHI signal triggers the sampling
357 * timer, but further sample-and-conversions are performed
358 * automatically as soon as the prior conversion is completed. */
359 REF2_5V_t REF2_5V; /*! Reference generator voltage. REFON must also be set.
360 * 0 1.5V
361 * 1 2.5V */
362 REFON_t REFON; /*! Reference generator on
363 * 0 Reference off
364 * 1 Reference on */
365 ADC12ON_t ADC12ON; /*! ADC12 on
366 * 0 ADC12 off
367 * 1 ADC12 on */
368 ADC12OVIE_t ADC12OVIE; /*! ADC12MEMx overflow-interrupt enable. The GIE bit must also be
369 * set to enable the interrupt.
370 * 0 Overflow interrupt disabled
371 * 1 Overflow interrupt enabled */
372 ADC12TOVIE_t ADC12TOVIE; /*! ADC12 conversion-time-overflow interrupt enable.
373 * The GIE bit must also be set to enable the interrupt.
374 * 0 Conversion time overflow interrupt disabled
375 * 1 Conversion time overflow interrupt enabled */
376 ENC_t ENC; /*! Enable conversion
377 * 0 ADC12 disabled
378 * 1 ADC12 enabled */
379 ADC12SC_t ADC12SC; /*! Start conversion. Software-controlled sample-and-conversion start.
380 * ADC12SC and ENC may be set together with one instruction. ADC12SC is
381 * reset automatically.
382 * 0 No sample-and-conversion-start
383 * 1 Start sample-and-conversion */
384 };
385
386 /*! ADC12 Control Register 1 */
387 struct ADC12CTL1_t {
388 CSTARTADD_t CSTARTADD; /*! Conversion start address. These bits select which ADC12
389 * conversion-memory register is used for a single conversion or for the first
390 * conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
391 * corresponding to ADC12MEM0 to ADC12MEM15. */
392 SHS_t SHS; /*! Sample-and-hold source select
393 * 00 ADC12SC bit
394 * 01 Timer_A.OUT1
395 * 10 Timer_B.OUT0
396 * 11 Timer_B.OUT1 */
397 SHP_t SHP; /*! Sample-and-hold pulse-mode select. This bit selects the source of the
398 * sampling signal (SAMPCON) to be either the output of the sampling timer or
399 * the sample-input signal directly.
400 * 0 SAMPCON signal is sourced from the sample-input signal.
401 * 1 SAMPCON signal is sourced from the sampling timer. */
402 ISSH_t ISSH; /*! Invert signal sample-and-hold
403 * 0 The sample-input signal is not inverted.
404 * 1 The sample-input signal is inverted. */
405 ADC12DIV_t ADC12DIV; /*! ADC12 clock divider
406 * 000 /1
407 * 001 /2
408 * 010 /3
409 * 011 /4
410 * 100 /5
411 * 101 /6
412 * 110 /7
413 * 111 /8 */
414 ADC12SSEL_t ADC12SSEL; /*! ADC12 clock source select
415 * 00 ADC12OSC
416 * 01 ACLK
417 * 10 MCLK
418 * 11 SMCLK */
419 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
420 * 00 Single-channel, single-conversion
421 * 01 Sequence-of-channels
422 * 10 Repeat-single-channel
423 * 11 Repeat-sequence-of-channels */
424 ADC12BUSY_t ADC12BUSY; /*! ADC12 busy. This bit indicates an active sample or conversion operation.
425 * 0 No operation is active.
426 * 1 A sequence, sample, or conversion is active. */
427 };
428
429 /*! ADC12 Conversion Memory Control Registers */
430 struct ADC12MCTL_t {
431 EOS_t EOS; /*! End of sequence. Indicates the last conversion in a sequence.
432 * 0 Not end of sequence
433 * 1 End of sequence */
434 SREF_t SREF; /*! Select reference
435 * 000 VR+ = AVCC and VR-- = AVSS
436 * 001 VR+ = VREF+ and VR-- = AVSS
437 * 010 VR+ = VeREF+ and VR-- = AVSS
438 * 011 VR+ = VeREF+ and VR-- = AVSS
439 * 100 VR+ = AVCC and VR-- = VREF--/ VeREF--
440 * 101 VR+ = VREF+ and VR-- = VREF--/ VeREF--
441 * 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF--
442 * 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
443 INCH_t INCH; /*! Input channel select
444 * 0000 A0
445 * 0001 A1
446 * 0010 A2
447 * 0011 A3
448 * 0100 A4
449 * 0101 A5
450 * 0110 A6
451 * 0111 A7
452 * 1000 VeREF+
453 * 1001 VREF--/VeREF--
454 * 1010 Temperature diode
455 * 1011 (AVCC ??? AVSS) / 2
456 * 1100 GND
457 * 1101 GND
458 * 1110 GND
459 * 1111 GND */
460 };
461
462 /*! ADC12 Interrupt Enable Register */
463 struct ADC12IE_t {
464 ADC12IE15_t ADC12IE15; /*! Enable or disable the interrupt request for the ADC12IFG15 bit.
465 * 0 Interrupt disabled
466 * 1 Interrupt enabled */
467 ADC12IE14_t ADC12IE14; /*! Enable or disable the interrupt request for the ADC12IFG14 bit.
468 * 0 Interrupt disabled
469 * 1 Interrupt enabled */
470 ADC12IE13_t ADC12IE13; /*! Enable or disable the interrupt request for the ADC12IFG13 bit.
471 * 0 Interrupt disabled
472 * 1 Interrupt enabled */
473 ADC12IE12_t ADC12IE12; /*! Enable or disable the interrupt request for the ADC12IFG12 bit.
474 * 0 Interrupt disabled
475 * 1 Interrupt enabled */
476 ADC12IE11_t ADC12IE11; /*! Enable or disable the interrupt request for the ADC12IFG11 bit.
477 * 0 Interrupt disabled
478 * 1 Interrupt enabled */
479 ADC12IE10_t ADC12IE10; /*! Enable or disable the interrupt request for the ADC12IFG10 bit.
480 * 0 Interrupt disabled
481 * 1 Interrupt enabled */
482 ADC12IE9_t ADC12IE9; /*! Enable or disable the interrupt request for the ADC12IFG9 bit.
483 * 0 Interrupt disabled
484 * 1 Interrupt enabled */
485 ADC12IE8_t ADC12IE8; /*! Enable or disable the interrupt request for the ADC12IFG8 bit.
486 * 0 Interrupt disabled
487 * 1 Interrupt enabled */
488 ADC12IE7_t ADC12IE7; /*! Enable or disable the interrupt request for the ADC12IFG7 bit.
489 * 0 Interrupt disabled
490 * 1 Interrupt enabled */
491 ADC12IE6_t ADC12IE6; /*! Enable or disable the interrupt request for the ADC12IFG6 bit.
492 * 0 Interrupt disabled
493 * 1 Interrupt enabled */
494 ADC12IE5_t ADC12IE5; /*! Enable or disable the interrupt request for the ADC12IFG5 bit.
495 * 0 Interrupt disabled
496 * 1 Interrupt enabled */
497 ADC12IE4_t ADC12IE4; /*! Enable or disable the interrupt request for the ADC12IFG4 bit.
498 * 0 Interrupt disabled
499 * 1 Interrupt enabled */
500 ADC12IE3_t ADC12IE3; /*! Enable or disable the interrupt request for the ADC12IFG3 bit.
501 * 0 Interrupt disabled
502 * 1 Interrupt enabled */
503 ADC12IE2_t ADC12IE2; /*! Enable or disable the interrupt request for the ADC12IFG2 bit.
504 * 0 Interrupt disabled
505 * 1 Interrupt enabled */
506 ADC12IE1_t ADC12IE1; /*! Enable or disable the interrupt request for the ADC12IFG1 bit.
507 * 0 Interrupt disabled
508 * 1 Interrupt enabled */
509 ADC12IE0_t ADC12IE0; /*! Enable or disable the interrupt request for the ADC12IFG0 bit.
510 * 0 Interrupt disabled
511 * 1 Interrupt enabled */
512 };
513
514 instance:
515 /*! ADC12CTL0 Register */
516 config ADC12CTL0_t ADC12CTL0 = {
517 ADC12SHT1 : SHT1_0,
518 ADC12SHT0 : SHT0_0,
519 MSC : MSC_OFF,
520 REF2_5V : REF2_5V_OFF,
521 REFON : REFON_OFF,
522 ADC12ON : ADC12ON_OFF,
523 ADC12OVIE : ADC12OVIE_OFF,
524 ADC12TOVIE : ADC12TOVIE_OFF,
525 ENC : ENC_OFF,
526 ADC12SC : ADC12SC_OFF
527 };
528
529 /*! ADC12CTL1 Register */
530 config ADC12CTL1_t ADC12CTL1 = {
531 CSTARTADD : CSTARTADD_0,
532 SHS : SHS_0,
533 SHP : SHP_OFF,
534 ISSH : ISSH_OFF,
535 ADC12DIV : ADC12DIV_0,
536 ADC12SSEL : ADC12SSEL_0,
537 CONSEQ : CONSEQ_0,
538 ADC12BUSY : ADC12BUSY_OFF
539 };
540
541 /*! ADC12MCTL0 Register */
542 config ADC12MCTL_t ADC12MCTL0 = {
543 EOS : EOS_OFF,
544 SREF : SREF_0,
545 INCH : INCH_0
546 };
547
548 /*! ADC12MCTL1 Register */
549 config ADC12MCTL_t ADC12MCTL1 = {
550 EOS : EOS_OFF,
551 SREF : SREF_0,
552 INCH : INCH_0
553 };
554
555 /*! ADC12MCTL2 Register */
556 config ADC12MCTL_t ADC12MCTL2 = {
557 EOS : EOS_OFF,
558 SREF : SREF_0,
559 INCH : INCH_0
560 };
561
562 /*! ADC12MCTL3 Register */
563 config ADC12MCTL_t ADC12MCTL3 = {
564 EOS : EOS_OFF,
565 SREF : SREF_0,
566 INCH : INCH_0
567 };
568
569 /*! ADC12MCTL4 Register */
570 config ADC12MCTL_t ADC12MCTL4 = {
571 EOS : EOS_OFF,
572 SREF : SREF_0,
573 INCH : INCH_0
574 };
575
576 /*! ADC12MCTL5 Register */
577 config ADC12MCTL_t ADC12MCTL5 = {
578 EOS : EOS_OFF,
579 SREF : SREF_0,
580 INCH : INCH_0
581 };
582
583 /*! ADC12MCTL6 Register */
584 config ADC12MCTL_t ADC12MCTL6 = {
585 EOS : EOS_OFF,
586 SREF : SREF_0,
587 INCH : INCH_0
588 };
589
590 /*! ADC12MCTL7 Register */
591 config ADC12MCTL_t ADC12MCTL7 = {
592 EOS : EOS_OFF,
593 SREF : SREF_0,
594 INCH : INCH_0
595 };
596
597 /*! ADC12MCTL8 Register */
598 config ADC12MCTL_t ADC12MCTL8 = {
599 EOS : EOS_OFF,
600 SREF : SREF_0,
601 INCH : INCH_0
602 };
603
604 /*! ADC12MCTL9 Register */
605 config ADC12MCTL_t ADC12MCTL9 = {
606 EOS : EOS_OFF,
607 SREF : SREF_0,
608 INCH : INCH_0
609 };
610
611 /*! ADC12MCTL10 Register */
612 config ADC12MCTL_t ADC12MCTL10 = {
613 EOS : EOS_OFF,
614 SREF : SREF_0,
615 INCH : INCH_0
616 };
617
618 /*! ADC12MCTL11 Register */
619 config ADC12MCTL_t ADC12MCTL11 = {
620 EOS : EOS_OFF,
621 SREF : SREF_0,
622 INCH : INCH_0
623 };
624
625 /*! ADC12MCTL12 Register */
626 config ADC12MCTL_t ADC12MCTL12 = {
627 EOS : EOS_OFF,
628 SREF : SREF_0,
629 INCH : INCH_0
630 };
631
632 /*! ADC12MCTL13 Register */
633 config ADC12MCTL_t ADC12MCTL13 = {
634 EOS : EOS_OFF,
635 SREF : SREF_0,
636 INCH : INCH_0
637 };
638
639 /*! ADC12MCTL14 Register */
640 config ADC12MCTL_t ADC12MCTL14 = {
641 EOS : EOS_OFF,
642 SREF : SREF_0,
643 INCH : INCH_0
644 };
645
646 /*! ADC12MCTL15 Register */
647 config ADC12MCTL_t ADC12MCTL15 = {
648 EOS : EOS_OFF,
649 SREF : SREF_0,
650 INCH : INCH_0
651 };
652
653 /*! ADC12 Interrupt Enable Register */
654 config ADC12IE_t ADC12IE = {
655 ADC12IE15 : ADC12IE15_OFF,
656 ADC12IE14 : ADC12IE14_OFF,
657 ADC12IE13 : ADC12IE13_OFF,
658 ADC12IE12 : ADC12IE12_OFF,
659 ADC12IE11 : ADC12IE11_OFF,
660 ADC12IE10 : ADC12IE10_OFF,
661 ADC12IE9 : ADC12IE9_OFF,
662 ADC12IE8 : ADC12IE8_OFF,
663 ADC12IE7 : ADC12IE7_OFF,
664 ADC12IE6 : ADC12IE6_OFF,
665 ADC12IE5 : ADC12IE5_OFF,
666 ADC12IE4 : ADC12IE4_OFF,
667 ADC12IE3 : ADC12IE3_OFF,
668 ADC12IE2 : ADC12IE2_OFF,
669 ADC12IE1 : ADC12IE1_OFF,
670 ADC12IE0 : ADC12IE0_OFF
671 };
672
673
674 /*! ADC12MEM0 Register */
675 config Bits16 ADC12MEM0 = 0;
676
677 /*! ADC12MEM1 Register */
678 config Bits16 ADC12MEM1 = 0;
679
680 /*! ADC12MEM2 Register */
681 config Bits16 ADC12MEM2 = 0;
682
683 /*! ADC12MEM3 Register */
684 config Bits16 ADC12MEM3 = 0;
685
686 /*! ADC12MEM4 Register */
687 config Bits16 ADC12MEM4 = 0;
688
689 /*! ADC12MEM5 Register */
690 config Bits16 ADC12MEM5 = 0;
691
692 /*! ADC12MEM6 Register */
693 config Bits16 ADC12MEM6 = 0;
694
695 /*! ADC12MEM7 Register */
696 config Bits16 ADC12MEM7 = 0;
697
698 /*! ADC12MEM8 Register */
699 config Bits16 ADC12MEM8 = 0;
700
701 /*! ADC12MEM9 Register */
702 config Bits16 ADC12MEM9 = 0;
703
704 /*! ADC12MEM10 Register */
705 config Bits16 ADC12MEM10 = 0;
706
707 /*! ADC12MEM11 Register */
708 config Bits16 ADC12MEM11 = 0;
709
710 /*! ADC12MEM12 Register */
711 config Bits16 ADC12MEM12 = 0;
712
713 /*! ADC12MEM13 Register */
714 config Bits16 ADC12MEM13 = 0;
715
716 /*! ADC12MEM14 Register */
717 config Bits16 ADC12MEM14 = 0;
718
719 /*! ADC12MEM15 Register */
720 config Bits16 ADC12MEM15 = 0;
721
722 /*! ADC12IV Register */
723 config Bits16 ADC12IV = ADC12IV_NONE;
724
725 /*! ADC12IFG Register */
726 config Bits16 ADC12IFG = 0;
727
728 /*! Determine if each Register needs to be forced set or not */
729 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
730 [
731 { register : "ADC12CTL0" , regForceSet : false },
732 { register : "ADC12CTL1" , regForceSet : false },
733 { register : "ADC12IFG" , regForceSet : false },
734 { register : "ADC12IV" , regForceSet : false },
735 { register : "ADC12IE" , regForceSet : false },
736 { register : "ADC12MCTL0" , regForceSet : false },
737 { register : "ADC12MCTL1" , regForceSet : false },
738 { register : "ADC12MCTL2" , regForceSet : false },
739 { register : "ADC12MCTL3" , regForceSet : false },
740 { register : "ADC12MCTL4" , regForceSet : false },
741 { register : "ADC12MCTL5" , regForceSet : false },
742 { register : "ADC12MCTL6" , regForceSet : false },
743 { register : "ADC12MCTL7" , regForceSet : false },
744 { register : "ADC12MCTL8" , regForceSet : false },
745 { register : "ADC12MCTL9" , regForceSet : false },
746 { register : "ADC12MCTL10" , regForceSet : false },
747 { register : "ADC12MCTL11" , regForceSet : false },
748 { register : "ADC12MCTL12" , regForceSet : false },
749 { register : "ADC12MCTL13" , regForceSet : false },
750 { register : "ADC12MCTL14" , regForceSet : false },
751 { register : "ADC12MCTL15" , regForceSet : false },
752 { register : "ADC12MEM0" , regForceSet : false },
753 { register : "ADC12MEM1" , regForceSet : false },
754 { register : "ADC12MEM2" , regForceSet : false },
755 { register : "ADC12MEM3" , regForceSet : false },
756 { register : "ADC12MEM4" , regForceSet : false },
757 { register : "ADC12MEM5" , regForceSet : false },
758 { register : "ADC12MEM6" , regForceSet : false },
759 { register : "ADC12MEM7" , regForceSet : false },
760 { register : "ADC12MEM8" , regForceSet : false },
761 { register : "ADC12MEM9" , regForceSet : false },
762 { register : "ADC12MEM10" , regForceSet : false },
763 { register : "ADC12MEM11" , regForceSet : false },
764 { register : "ADC12MEM12" , regForceSet : false },
765 { register : "ADC12MEM13" , regForceSet : false },
766 { register : "ADC12MEM14" , regForceSet : false },
767 { register : "ADC12MEM15" , regForceSet : false },
768 ];
769 }