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12
13 14 15 16
17
18 package ti.catalog.arm.cortexm3.lm3init;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Stellaris M3 Boot Support.
25 *
26 * The Boot module supports boot initialization for the Stellaris M3 devices.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 metaonly struct ModuleView {
45 Bool configureClock;
46 Bool sysClockDivEnable;
47 String sysClockDiv;
48 Bool pwmClockDivEnable;
49 String pwmClockDiv;
50 String xtal;
51 String oscSrc;
52 Bool pllBypass;
53 Bool pllOutEnable;
54 Bool ioscDisable;
55 Bool moscDisable;
56 Bool configureLdo;
57 String ldoOut;
58 }
59
60 @Facet
61 metaonly config ViewInfo.Instance rovViewInfo =
62 ViewInfo.create({
63 viewMap: [
64 [
65 'Module',
66 {
67 type: ViewInfo.MODULE,
68 viewInitFxn: 'viewInitModule',
69 structName: 'ModuleView'
70 }
71 ],
72 ]
73 });
74
75
76 enum SysDiv {
77 SYSDIV_1 = 0x07800000, /*! Processor clock is osc/pll /1 */
78 SYSDIV_2 = 0x00C00000, /*! Processor clock is osc/pll /2 */
79 SYSDIV_3 = 0x01400000, /*! Processor clock is osc/pll /3 */
80 SYSDIV_4 = 0x01C00000, /*! Processor clock is osc/pll /4 */
81 SYSDIV_5 = 0x02400000, /*! Processor clock is osc/pll /5 */
82 SYSDIV_6 = 0x02C00000, /*! Processor clock is osc/pll /6 */
83 SYSDIV_7 = 0x03400000, /*! Processor clock is osc/pll /7 */
84 SYSDIV_8 = 0x03C00000, /*! Processor clock is osc/pll /8 */
85 SYSDIV_9 = 0x04400000, /*! Processor clock is osc/pll /9 */
86 SYSDIV_10 = 0x04C00000, /*! Processor clock is osc/pll /10 */
87 SYSDIV_11 = 0x05400000, /*! Processor clock is osc/pll /11 */
88 SYSDIV_12 = 0x05C00000, /*! Processor clock is osc/pll /12 */
89 SYSDIV_13 = 0x06400000, /*! Processor clock is osc/pll /13 */
90 SYSDIV_14 = 0x06C00000, /*! Processor clock is osc/pll /14 */
91 SYSDIV_15 = 0x07400000, /*! Processor clock is osc/pll /15 */
92 SYSDIV_16 = 0x07C00000, /*! Processor clock is osc/pll /16 */
93 SYSDIV_17 = 0x88400000, /*! Processor clock is osc/pll /17 */
94 SYSDIV_18 = 0x88C00000, /*! Processor clock is osc/pll /18 */
95 SYSDIV_19 = 0x89400000, /*! Processor clock is osc/pll /19 */
96 SYSDIV_20 = 0x89C00000, /*! Processor clock is osc/pll /20 */
97 SYSDIV_21 = 0x8A400000, /*! Processor clock is osc/pll /21 */
98 SYSDIV_22 = 0x8AC00000, /*! Processor clock is osc/pll /22 */
99 SYSDIV_23 = 0x8B400000, /*! Processor clock is osc/pll /23 */
100 SYSDIV_24 = 0x8BC00000, /*! Processor clock is osc/pll /24 */
101 SYSDIV_25 = 0x8C400000, /*! Processor clock is osc/pll /25 */
102 SYSDIV_26 = 0x8CC00000, /*! Processor clock is osc/pll /26 */
103 SYSDIV_27 = 0x8D400000, /*! Processor clock is osc/pll /27 */
104 SYSDIV_28 = 0x8DC00000, /*! Processor clock is osc/pll /28 */
105 SYSDIV_29 = 0x8E400000, /*! Processor clock is osc/pll /29 */
106 SYSDIV_30 = 0x8EC00000, /*! Processor clock is osc/pll /30 */
107 SYSDIV_31 = 0x8F400000, /*! Processor clock is osc/pll /31 */
108 SYSDIV_32 = 0x8FC00000, /*! Processor clock is osc/pll /32 */
109 SYSDIV_33 = 0x90400000, /*! Processor clock is osc/pll /33 */
110 SYSDIV_34 = 0x90C00000, /*! Processor clock is osc/pll /34 */
111 SYSDIV_35 = 0x91400000, /*! Processor clock is osc/pll /35 */
112 SYSDIV_36 = 0x91C00000, /*! Processor clock is osc/pll /36 */
113 SYSDIV_37 = 0x92400000, /*! Processor clock is osc/pll /37 */
114 SYSDIV_38 = 0x92C00000, /*! Processor clock is osc/pll /38 */
115 SYSDIV_39 = 0x93400000, /*! Processor clock is osc/pll /39 */
116 SYSDIV_40 = 0x93C00000, /*! Processor clock is osc/pll /40 */
117 SYSDIV_41 = 0x94400000, /*! Processor clock is osc/pll /41 */
118 SYSDIV_42 = 0x94C00000, /*! Processor clock is osc/pll /42 */
119 SYSDIV_43 = 0x95400000, /*! Processor clock is osc/pll /43 */
120 SYSDIV_44 = 0x95C00000, /*! Processor clock is osc/pll /44 */
121 SYSDIV_45 = 0x96400000, /*! Processor clock is osc/pll /45 */
122 SYSDIV_46 = 0x96C00000, /*! Processor clock is osc/pll /46 */
123 SYSDIV_47 = 0x97400000, /*! Processor clock is osc/pll /47 */
124 SYSDIV_48 = 0x97C00000, /*! Processor clock is osc/pll /48 */
125 SYSDIV_49 = 0x98400000, /*! Processor clock is osc/pll /49 */
126 SYSDIV_50 = 0x98C00000, /*! Processor clock is osc/pll /50 */
127 SYSDIV_51 = 0x99400000, /*! Processor clock is osc/pll /51 */
128 SYSDIV_52 = 0x99C00000, /*! Processor clock is osc/pll /52 */
129 SYSDIV_53 = 0x9A400000, /*! Processor clock is osc/pll /53 */
130 SYSDIV_54 = 0x9AC00000, /*! Processor clock is osc/pll /54 */
131 SYSDIV_55 = 0x9B400000, /*! Processor clock is osc/pll /55 */
132 SYSDIV_56 = 0x9BC00000, /*! Processor clock is osc/pll /56 */
133 SYSDIV_57 = 0x9C400000, /*! Processor clock is osc/pll /57 */
134 SYSDIV_58 = 0x9CC00000, /*! Processor clock is osc/pll /58 */
135 SYSDIV_59 = 0x9D400000, /*! Processor clock is osc/pll /59 */
136 SYSDIV_60 = 0x9DC00000, /*! Processor clock is osc/pll /60 */
137 SYSDIV_61 = 0x9E400000, /*! Processor clock is osc/pll /61 */
138 SYSDIV_62 = 0x9EC00000, /*! Processor clock is osc/pll /62 */
139 SYSDIV_63 = 0x9F400000, /*! Processor clock is osc/pll /63 */
140 SYSDIV_64 = 0x9FC00000, /*! Processor clock is osc/pll /64 */
141 SYSDIV_2_5 = 0xC1000000, /*! Processor clock is pll / 2.5 */
142 SYSDIV_3_5 = 0xC1800000, /*! Processor clock is pll / 3.5 */
143 SYSDIV_4_5 = 0xC2000000, /*! Processor clock is pll / 4.5 */
144 SYSDIV_5_5 = 0xC2800000, /*! Processor clock is pll / 5.5 */
145 SYSDIV_6_5 = 0xC3000000, /*! Processor clock is pll / 6.5 */
146 SYSDIV_7_5 = 0xC3800000, /*! Processor clock is pll / 7.5 */
147 SYSDIV_8_5 = 0xC4000000, /*! Processor clock is pll / 8.5 */
148 SYSDIV_9_5 = 0xC4800000, /*! Processor clock is pll / 9.5 */
149 SYSDIV_10_5 = 0xC5000000, /*! Processor clock is pll / 10.5 */
150 SYSDIV_11_5 = 0xC5800000, /*! Processor clock is pll / 11.5 */
151 SYSDIV_12_5 = 0xC6000000, /*! Processor clock is pll / 12.5 */
152 SYSDIV_13_5 = 0xC6800000, /*! Processor clock is pll / 13.5 */
153 SYSDIV_14_5 = 0xC7000000, /*! Processor clock is pll / 14.5 */
154 SYSDIV_15_5 = 0xC7800000, /*! Processor clock is pll / 15.5 */
155 SYSDIV_16_5 = 0xC8000000, /*! Processor clock is pll / 16.5 */
156 SYSDIV_17_5 = 0xC8800000, /*! Processor clock is pll / 17.5 */
157 SYSDIV_18_5 = 0xC9000000, /*! Processor clock is pll / 18.5 */
158 SYSDIV_19_5 = 0xC9800000, /*! Processor clock is pll / 19.5 */
159 SYSDIV_20_5 = 0xCA000000, /*! Processor clock is pll / 20.5 */
160 SYSDIV_21_5 = 0xCA800000, /*! Processor clock is pll / 21.5 */
161 SYSDIV_22_5 = 0xCB000000, /*! Processor clock is pll / 22.5 */
162 SYSDIV_23_5 = 0xCB800000, /*! Processor clock is pll / 23.5 */
163 SYSDIV_24_5 = 0xCC000000, /*! Processor clock is pll / 24.5 */
164 SYSDIV_25_5 = 0xCC800000, /*! Processor clock is pll / 25.5 */
165 SYSDIV_26_5 = 0xCD000000, /*! Processor clock is pll / 26.5 */
166 SYSDIV_27_5 = 0xCD800000, /*! Processor clock is pll / 27.5 */
167 SYSDIV_28_5 = 0xCE000000, /*! Processor clock is pll / 28.5 */
168 SYSDIV_29_5 = 0xCE800000, /*! Processor clock is pll / 29.5 */
169 SYSDIV_30_5 = 0xCF000000, /*! Processor clock is pll / 30.5 */
170 SYSDIV_31_5 = 0xCF800000, /*! Processor clock is pll / 31.5 */
171 SYSDIV_32_5 = 0xD0000000, /*! Processor clock is pll / 32.5 */
172 SYSDIV_33_5 = 0xD0800000, /*! Processor clock is pll / 33.5 */
173 SYSDIV_34_5 = 0xD1000000, /*! Processor clock is pll / 34.5 */
174 SYSDIV_35_5 = 0xD1800000, /*! Processor clock is pll / 35.5 */
175 SYSDIV_36_5 = 0xD2000000, /*! Processor clock is pll / 36.5 */
176 SYSDIV_37_5 = 0xD2800000, /*! Processor clock is pll / 37.5 */
177 SYSDIV_38_5 = 0xD3000000, /*! Processor clock is pll / 38.5 */
178 SYSDIV_39_5 = 0xD3800000, /*! Processor clock is pll / 39.5 */
179 SYSDIV_40_5 = 0xD4000000, /*! Processor clock is pll / 40.5 */
180 SYSDIV_41_5 = 0xD4800000, /*! Processor clock is pll / 41.5 */
181 SYSDIV_42_5 = 0xD5000000, /*! Processor clock is pll / 42.5 */
182 SYSDIV_43_5 = 0xD5800000, /*! Processor clock is pll / 43.5 */
183 SYSDIV_44_5 = 0xD6000000, /*! Processor clock is pll / 44.5 */
184 SYSDIV_45_5 = 0xD6800000, /*! Processor clock is pll / 45.5 */
185 SYSDIV_46_5 = 0xD7000000, /*! Processor clock is pll / 46.5 */
186 SYSDIV_47_5 = 0xD7800000, /*! Processor clock is pll / 47.5 */
187 SYSDIV_48_5 = 0xD8000000, /*! Processor clock is pll / 48.5 */
188 SYSDIV_49_5 = 0xD8800000, /*! Processor clock is pll / 49.5 */
189 SYSDIV_50_5 = 0xD9000000, /*! Processor clock is pll / 50.5 */
190 SYSDIV_51_5 = 0xD9800000, /*! Processor clock is pll / 51.5 */
191 SYSDIV_52_5 = 0xDA000000, /*! Processor clock is pll / 52.5 */
192 SYSDIV_53_5 = 0xDA800000, /*! Processor clock is pll / 53.5 */
193 SYSDIV_54_5 = 0xDB000000, /*! Processor clock is pll / 54.5 */
194 SYSDIV_55_5 = 0xDB800000, /*! Processor clock is pll / 55.5 */
195 SYSDIV_56_5 = 0xDC000000, /*! Processor clock is pll / 56.5 */
196 SYSDIV_57_5 = 0xDC800000, /*! Processor clock is pll / 57.5 */
197 SYSDIV_58_5 = 0xDD000000, /*! Processor clock is pll / 58.5 */
198 SYSDIV_59_5 = 0xDD800000, /*! Processor clock is pll / 59.5 */
199 SYSDIV_60_5 = 0xDE000000, /*! Processor clock is pll / 60.5 */
200 SYSDIV_61_5 = 0xDE800000, /*! Processor clock is pll / 61.5 */
201 SYSDIV_62_5 = 0xDF000000, /*! Processor clock is pll / 62.5 */
202 SYSDIV_63_5 = 0xDF800000 /*! Processor clock is pll / 63.5 */
203 }
204
205 enum PwmDiv {
206 PWMDIV_1 = 0x00000000, /*! PWM clock /1 */
207 PWMDIV_2 = 0x00100000, /*! PWM clock /2 */
208 PWMDIV_4 = 0x00120000, /*! PWM clock /4 */
209 PWMDIV_8 = 0x00140000, /*! PWM clock /8 */
210 PWMDIV_16 = 0x00160000, /*! PWM clock /16 */
211 PWMDIV_32 = 0x00180000, /*! PWM clock /32 */
212 PWMDIV_64 = 0x001A0000 /*! PWM clock /64 */
213 }
214
215 enum XtalFreq {
216 XTAL_1MHZ = 0x00000000, /*! Using a 1MHz crystal */
217 XTAL_1_84MHZ = 0x00000040, /*! Using a 1.8432MHz crystal */
218 XTAL_2MHZ = 0x00000080, /*! Using a 2MHz crystal */
219 XTAL_2_45MHZ = 0x000000C0, /*! Using a 2.4576MHz crystal */
220 XTAL_3_57MHZ = 0x00000100, /*! Using a 3.579545MHz crystal */
221 XTAL_3_68MHZ = 0x00000140, /*! Using a 3.6864MHz crystal */
222 XTAL_4MHZ = 0x00000180, /*! Using a 4MHz crystal */
223 XTAL_4_09MHZ = 0x000001C0, /*! Using a 4.096MHz crystal */
224 XTAL_4_91MHZ = 0x00000200, /*! Using a 4.9152MHz crystal */
225 XTAL_5MHZ = 0x00000240, /*! Using a 5MHz crystal */
226 XTAL_5_12MHZ = 0x00000280, /*! Using a 5.12MHz crystal */
227 XTAL_6MHZ = 0x000002C0, /*! Using a 6MHz crystal */
228 XTAL_6_14MHZ = 0x00000300, /*! Using a 6.144MHz crystal */
229 XTAL_7_37MHZ = 0x00000340, /*! Using a 7.3728MHz crystal */
230 XTAL_8MHZ = 0x00000380, /*! Using a 8MHz crystal */
231 XTAL_8_19MHZ = 0x000003C0, /*! Using a 8.192MHz crystal */
232 XTAL_10MHZ = 0x00000400, /*! 10.0 MHz (USB) */
233 XTAL_12MHZ = 0x00000440, /*! 12.0 MHz (USB) */
234 XTAL_12_2MHZ = 0x00000480, /*! 12.288 MHz */
235 XTAL_13_5MHZ = 0x000004C0, /*! 13.56 MHz */
236 XTAL_14_3MHZ = 0x00000500, /*! 14.31818 MHz */
237 XTAL_16MHZ = 0x00000540, /*! 16.0 MHz (USB) */
238 XTAL_16_3MHZ = 0x00000580 /*! 16.384 MHz */
239 }
240
241 enum OscSrc {
242 OSCSRC_MAIN = 0x00000000, /*! Use the main oscillator */
243 OSCSRC_INT = 0x00000010, /*! Use the internal oscillator */
244 OSCSRC_INT4 = 0x00000020, /*! Use the internal oscillator / 4 */
245 OSCSRC_30 = 0x00000030 /*! 30 KHz internal oscillator */
246 }
247
248 enum LdoOut {
249 LDOPCTL_2_55V = 0x0000001F, /*! LDO output of 2.55V */
250 LDOPCTL_2_60V = 0x0000001E, /*! LDO output of 2.60V */
251 LDOPCTL_2_65V = 0x0000001D, /*! LDO output of 2.65V */
252 LDOPCTL_2_70V = 0x0000001C, /*! LDO output of 2.70V */
253 LDOPCTL_2_75V = 0x0000001B, /*! LDO output of 2.75V */
254 LDOPCTL_2_25V = 0x00000005, /*! LDO output of 2.25V */
255 LDOPCTL_2_30V = 0x00000004, /*! LDO output of 2.30V */
256 LDOPCTL_2_35V = 0x00000003, /*! LDO output of 2.35V */
257 LDOPCTL_2_40V = 0x00000002, /*! LDO output of 2.40V */
258 LDOPCTL_2_45V = 0x00000001, /*! LDO output of 2.45V */
259 LDOPCTL_2_50V = 0x00000000 /*! LDO output of 2.50V */
260 }
261
262 /*!
263 * Clock configuration flag, default is false.
264 *
265 * Set to true to automatically configure the Clock.
266 */
267 config Bool configureClock = false;
268
269 /*! SYS Clock Divisor */
270 config SysDiv sysClockDiv = SYSDIV_1;
271
272 /*! PWM Clock Divisor */
273 config PwmDiv pwmClockDiv = PWMDIV_1;
274
275 /*! Crystal Value */
276 config XtalFreq xtal = XTAL_1MHZ;
277
278 /*! Oscillator Source */
279 config OscSrc oscSrc = OSCSRC_MAIN;
280
281 /*! PLL Bypass flag */
282 config Bool pllBypass = false;
283
284 /*! PLL Output Enable flag */
285 config Bool pllOutEnable = false;
286
287 /*! Internal Oscillator Disable flag */
288 config Bool ioscDisable = false;
289
290 /*! Main Oscillator Disable flag */
291 config Bool moscDisable = false;
292
293 /*!
294 * LDO configuration flag, default is false.
295 *
296 * Set to true to automatically configure the LDO.
297 */
298 config Bool configureLdo = false;
299
300 /*!
301 * LDO VADJ setting, default is 2.5V
302 */
303 config LdoOut ldoOut = LDOPCTL_2_50V;
304
305 /*!
306 * @_nodoc
307 * computed RCC value based on settings
308 */
309 config UInt ulConfig;
310
311 /*!
312 * @_nodoc
313 * ======== getFrequency ========
314 * Gets the resulting output frequency (in Hz) given the Clock
315 * configuration parameters.
316 *
317 * Currently un-implemented.
318 */
319 UInt32 getFrequency();
320
321 /*!
322 * @_nodoc
323 * ======== registerFreqListener ========
324 * Register a module to be notified whenever the frequency changes.
325 *
326 * The registered module must have a function named 'fireFrequencyUpdate'
327 * which takes the new frequency as an argument.
328 */
329 function registerFreqListener();
330
331 };
332 333 334
335