1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2008 Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12 /*!
13 * Universal Serial Communication Interface
14 */
15 metaonlyinterface IUSCI_SPI inherits IUSCI {
16
17 //*****************************************************************
18 //* REGISTER BIT DEFINITIONS *
19 //*****************************************************************
20
21 /*! Clock phase select. */
22 enum UCCKPH_t {
23 UCCKPH_OFF = 0x00, /*! Data is changed on the first UCLK edge and captured on the following edge. */
24 UCCKPH = 0x80 /*! Data is captured on the first UCLK edge and changed on the following edge. */
25 };
26
27 /*! Clock polarity select. */
28 enum UCCKPL_t {
29 UCCKPL_OFF = 0x00, /*! Inactive state is low */
30 UCCKPL = 0x40 /*! Inactive state is high */
31 };
32
33 /*! Master mode select */
34 enum UCMST_t {
35 UCMST_OFF = 0x00, /*! Slave mode */
36 UCMST = 0x40 /*! Master mode */
37 };
38
39 /*! USCI clock source select. These bits select the BRCLK source clock. */
40 enum UCSSEL_SPI_t {
41 UCSSEL_0 = 0x00, /*! NA */
42 UCSSEL_1 = 0x01, /*! ACLK */
43 UCSSEL_2 = 0x02 /*! SMCLK */
44 /* UCSSEL_3 = 0x04 /*! SMCLK */
45 };
46
47 struct UCxCTL0_t {
48 UCCKPH_t UCCKPH; /*! Clock phase select.
49 * 0 Data is changed on the first UCLK edge and captured on the
50 * following edge.
51 * 1 Data is captured on the first UCLK edge and changed on the
52 * following edge. */
53 UCCKPL_t UCCKPL; /*! Clock polarity select
54 * 0 The inactive state is low
55 * 1 The inactive state is high */
56 UCMSB_t UCMSB; /*! MSB first select. Controls the direction of the receive and transmit shift
57 *register.
58 * 0 LSB first
59 * 1 MSB first */
60 UC7BIT_t UC7BIT; /*! Character length. Selects 7-bit or 8-bit character length.
61 * 0 8-bit data
62 * 1 7-bit data */
63 UCMST_t UCMST; /*! Master mode select
64 * 0 Slave mode
65 * 1 Master mode */
66 UCMODE_SYNC_t UCMODE; /*! USCI mode. The UCMODEx bits select the synchronous mode when
67 *UCSYNC = 1.
68 * 00 3-Pin SPI
69 * 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
70 * 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
71 * 11 I2C Mode */
72 UCSYNC_t UCSYNC; /*! Synchronous mode enable
73 * 0 Asynchronous mode
74 * 1 Synchronous Mode */
75 }
76
77 struct UCxCTL1_t {
78 UCSSEL_SPI_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock in
79 *master mode. UCxCLK is always used in slave mode.
80 * 00 NA
81 * 01 ACLK
82 * 10 SMCLK
83 * 11 SMCLK */
84 UCSWRST_t UCSWRST; /*! Software reset enable
85 * 0 Disabled. USCI reset released for operation.
86 * 1 Enabled. USCI logic held in reset state. */
87 }
88
89 struct UCxSTAT_t {
90 UCLISTEN_t UCLISTEN; /*! Listen enable. The UCLISTEN bit selects loopback mode.
91 * 0 Disabled
92 * 1 Enabled. UCAxTXD is internally fed back to the receiver. */
93 UCFE_t UCFE; /*! Framing error flag. This bit indicates a bus conflict in 4-wire master mode.
94 *UCFE is not used in 3-wire master or any slave mode.
95 * 0 No error
96 * 1 Bus conflict occurred */
97 UCOE_t UCOE; /*! Overrun error flag. This bit is set when a character is transferred into
98 *UCAxRXBUF before the previous character was read. UCOE is cleared
99 *automatically when UCxRXBUF is read, and must not be cleared by
100 *software. Otherwise, it will not function correctly.
101 * 0 No error
102 * 1 Overrun error occurred */
103 UCBUSY_t UCBUSY; /*! USCI busy. This bit indicates if a transmit or receive operation is in
104 *progress.
105 * 0 USCI inactive
106 * 1 USCI transmitting or receiving */
107 }
108 }