1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== SD16_A ========
14 * MSP430F2xx Family SD16_A Module
15 */
16 metaonly module SD16_A inherits ISD16 {
17
18
19 /*! SD16CTL Register */
20 struct SD16CTL_t {
21 SD16XDIV_t SD16XDIV; /*! SD16_A clock divider
22 * 000 Divide by 1
23 * 001 Divide by 3
24 * 010 Divide by 16
25 * 011 Divide by 48
26 * 1xx Reserved */
27 SD16LP_t SD16LP; /*! Low power mode. This bit selects a reduced speed, reduced power mode
28 * 0 Low-power mode is disabled
29 * 1 Low-power mode is enabled. The maximum clock frequency for the
30 * SD16_A is reduced. */
31 SD16DIV_t SD16DIV; /*! SD16_A clock divider
32 * 00 Divide by 1
33 * 01 Divide by 2
34 * 10 Divide by 4
35 * 11 Divide by 8 */
36 SD16SSEL_t SD16SSEL; /*! SD16_A clock source select
37 * 00 MCLK
38 * 01 SMCLK
39 * 10 ACLK
40 * External TACLK */
41 SD16VMIDON_t SD16VMIDON; /*! VMID buffer on
42 * 0 Off
43 * 1 On */
44 SD16REFON_t SD16REFON; /*! Reference generator on
45 * 0 Reference off
46 * 1 Reference on */
47 SD16OVIE_t SD16OVIE; /*! SD16_A overflow interrupt enable. The GIE bit must also be set to enable the
48 * interrupt.
49 * 0 Overflow interrupt disabled
50 * 1 Overflow interrupt enabled */
51 };
52
53 /*! SD16CCTL0 Register */
54 struct SD16CCTL0_t {
55 SD16UNI_t SD16UNI; /*! Unipolar mode select
56 * 0 Bipolar mode
57 * 1 Unipolar mode */
58 SD16XOSR_t SD16XOSR; /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
59 * select the oversampling ratio. See SD16OSRx bit description for settings. */
60 SD16SNGL_t SD16SNGL; /*! Single conversion mode select
61 * 0 Continuous conversion mode
62 * 1 Single conversion mode */
63 SD16OSR_t SD16OSR; /*! Oversampling ratio
64 * When SD16XOSR = 0
65 * 00 256
66 * 01 128
67 * 10 64
68 * 11 32
69 * When SD16XOSR = 1
70 * 00 512
71 * 01 1024
72 * 10 Reserved
73 * 11 Reserved */
74 SD16LSBTOG_t SD16LSBTOG; /*! LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time
75 * the SD16MEM0 register is read.
76 * 0 SD16LSBACC does not toggle with each SD16MEM0 read
77 * 1 SD16LSBACC toggles with each SD16MEM0 read */
78 SD16LSBACC_t SD16LSBACC; /*! LSB access. This bit allows access to the upper or lower 16-bits of the
79 * SD16_A conversion result.
80 * 0 SD16MEMx contains the most significant 16-bits of the conversion.
81 * 0 SD16MEMx contains the least significant 16-bits of the conversion. */
82 SD16OVIFG_t SD16OVIFG; /*! SD16_A overflow interrupt flag
83 * 0 No overflow interrupt pending
84 * 1 Overflow interrupt pending */
85 SD16DF_t SD16DF; /*! SD16_A data format
86 * 0 Offset binary
87 * 1 2's complement */
88 SD16IE_t SD16IE; /*! SD16_A interrupt enable
89 * 0 Disabled
90 * 1 Enabled */
91 SD16IFG_t SD16IFG; /*! SD16_A interrupt flag. SD16IFG is set when new conversion results are
92 * available. SD16IFG is automatically reset when the corresponding
93 * SD16MEMx register is read, or may be cleared with software.
94 * 0 No interrupt pending
95 * 1 Interrupt pending */
96 SD16SC_t SD16SC; /*! SD16_A start conversion
97 * 0 No conversion start
98 * 1 Start conversion */
99 };
100
101 /*! SD16INCTL0 Register */
102 struct SD16INCTL0_t {
103 SD16INTDLY_t SD16INTDLY; /*! Interrupt delay generation after conversion start. These bits select the
104 * delay for the first interrupt after conversion start.
105 * 00 Fourth sample causes interrupt
106 * 01 Third sample causes interrupt
107 * 10 Second sample causes interrupt
108 * 11 First sample causes interrupt */
109
110 SD16GAIN_t SD16GAIN; /*! SD16_A preamplifier gain
111 * 000 Multiply by 1
112 * 001 Multiply by 2
113 * 010 Multiply by 4
114 * 011 Multiply by 8
115 * 100 Multiply by 16
116 * 101 Multiply by 32
117 * 110 Reserved
118 * 111 Reserved */
119
120 SD16INCH_t SD16INCH; /*! SD16_A channel differential pair input
121 * 000 A0
122 * 001 A1
123 * 010 A2
124 * 011 A3
125 * 100 A4
126 * 101 A5-- (AVCC -- AVSS) / 11
127 * 110 A6 -- Temperature Sensor
128 * 111 A7 -- Short for PGA offset measurement */
129 };
130
131 /*! SD16_A Analog Input Enable Register */
132 struct SD16AE_t {
133 SD16AE0_t SD16AE0; /*! SD16_A analog enable
134 * 0 External input disabled. Negative inputs are internally connected to
135 * VSS.
136 * 1 External input enabled */
137 SD16AE1_t SD16AE1; /*! SD16_A analog enable
138 * 0 External input disabled. Negative inputs are internally connected to
139 * VSS.
140 * 1 External input enabled */
141 SD16AE2_t SD16AE2; /*! SD16_A analog enable
142 * 0 External input disabled. Negative inputs are internally connected to
143 * VSS.
144 * 1 External input enabled */
145 SD16AE3_t SD16AE3; /*! SD16_A analog enable
146 * 0 External input disabled. Negative inputs are internally connected to
147 * VSS.
148 * 1 External input enabled */
149 SD16AE4_t SD16AE4; /*! SD16_A analog enable
150 * 0 External input disabled. Negative inputs are internally connected to
151 * VSS.
152 * 1 External input enabled */
153 SD16AE5_t SD16AE5; /*! SD16_A analog enable
154 * 0 External input disabled. Negative inputs are internally connected to
155 * VSS.
156 * 1 External input enabled */
157 SD16AE6_t SD16AE6; /*! SD16_A analog enable
158 * 0 External input disabled. Negative inputs are internally connected to
159 * VSS.
160 * 1 External input enabled */
161 SD16AE7_t SD16AE7; /*! SD16_A analog enable
162 * 0 External input disabled. Negative inputs are internally connected to
163 * VSS.
164 * 1 External input enabled */
165 };
166
167 /*!
168 * ======== create ========
169 * Create an instance of this peripheral.
170 */
171 create();
172
173 instance:
174
175 /*! SD16CTL Register */
176 config SD16CTL_t SD16CTL = {
177 SD16XDIV : SD16XDIV_0,
178 SD16LP : SD16LP_OFF,
179 SD16DIV : SD16DIV_0,
180 SD16SSEL : SD16SSEL_0,
181 SD16VMIDON : SD16VMIDON_OFF,
182 SD16REFON : SD16REFON_OFF,
183 SD16OVIE : SD16OVIE_OFF
184 };
185
186 /*! SD16CCTL0 Register */
187 config SD16CCTL0_t SD16CCTL0 = {
188 SD16UNI : SD16UNI_OFF,
189 SD16XOSR : SD16XOSR_OFF,
190 SD16SNGL : SD16SNGL_OFF,
191 SD16OSR : SD16OSR_256,
192 SD16LSBTOG : SD16LSBTOG_OFF,
193 SD16LSBACC : SD16LSBACC_OFF,
194 SD16OVIFG : SD16OVIFG_OFF,
195 SD16DF : SD16DF_OFF,
196 SD16IE : SD16IE_OFF,
197 SD16IFG : SD16IFG_OFF,
198 SD16SC : SD16SC_OFF
199 };
200
201 /*! SD16INCTL0 Register */
202 config SD16INCTL0_t SD16INCTL0 = {
203 SD16INTDLY : SD16INTDLY_0,
204 SD16GAIN : SD16GAIN_1,
205 SD16INCH : SD16INCH_0
206 };
207
208 /*! SD16AE Register */
209 config SD16AE_t SD16AE = {
210 SD16AE0 : SD16AE0_OFF,
211 SD16AE1 : SD16AE1_OFF,
212 SD16AE2 : SD16AE2_OFF,
213 SD16AE3 : SD16AE3_OFF,
214 SD16AE4 : SD16AE4_OFF,
215 SD16AE5 : SD16AE5_OFF,
216 SD16AE6 : SD16AE6_OFF,
217 SD16AE7 : SD16AE7_OFF
218 };
219
220 /*! SD16IV Register */
221 config Bits16 SD16IV = SD16IV_SD16OVIFG_OFF;
222
223 /*! SD16MEM0 Register */
224 config Bits16 SD16MEM0 = SD16IV_SD16MEM0_OFF;
225
226 /*! Determine if each Register needs to be forced set or not */
227 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
228 [
229 { register : "SD16CTL" , regForceSet : false },
230 { register : "SD16CCTL0" , regForceSet : false },
231 { register : "SD16INCTL0" , regForceSet : false },
232 { register : "SD16AE" , regForceSet : false },
233 { register : "SD16IV" , regForceSet : false },
234 { register : "SD16MEM0" , regForceSet : false }
235 ];
236
237 }