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12
13 /*!
14 * ======== ISD16 ========
15 * MSP430 ISD16 interface
16 */
17 metaonly interface ISD16 inherits xdc.platform.IPeripheral {
18
19 /*! SD16XDIVx Bits */
20 enum SD16XDIV_t {
21 SD16XDIV_0 = 0x000, /*! Divide by 1 */
22 SD16XDIV_1 = 0x200, /*! Divide by 3 */
23 SD16XDIV_2 = 0x400, /*! Divide by 16 */
24 SD16XDIV_3 = 0x800 /*! Divide by 48 */
25 };
26
27 /*! SD16LP Bit */
28 enum SD16LP_t {
29 SD16LP_OFF = 0x000, /*! Low-power mode is disabled */
30 SD16LP = 0x100 /*! Low-power mode is enabled. The maximum clock frequency for the SD16_A is reduced */
31 };
32
33 /*! SD16DIVx Bits */
34 enum SD16DIV_t {
35 SD16DIV_0 = 0x00, /*! Divide by 1 */
36 SD16DIV_1 = 0x40, /*! Divide by 2 */
37 SD16DIV_2 = 0x80, /*! Divide by 4 */
38 SD16DIV_3 = 0xC0 /*! Divide by 8 */
39 };
40
41 /*! SD16SSELx Bits */
42 enum SD16SSEL_t {
43 SD16SSEL_0 = 0x00, /*! MCLK */
44 SD16SSEL_1 = 0x10, /*! SMCLK */
45 SD16SSEL_2 = 0x20, /*! ACLK */
46 SD16SSEL_3 = 0x30 /*! External TACLK */
47 };
48
49 /*! SD16VMIDON Bit */
50 enum SD16VMIDON_t {
51 SD16VMIDON_OFF = 0x00, /*! Off */
52 SD16VMIDON = 0x08 /*! On */
53 };
54
55 /*! SD16REFON Bit */
56 enum SD16REFON_t {
57 SD16REFON_OFF = 0x00, /*! Reference off */
58 SD16REFON = 0x04 /*! Reference on */
59 };
60
61 /*! SD16OVIE Bit */
62 enum SD16OVIE_t {
63 SD16OVIE_OFF = 0x00, /*! Overflow interrupt disabled */
64 SD16OVIE = 0x02 /*! Overflow interrupt enabled */
65 };
66
67 /*! SD16BUFx Bits */
68 enum SD16BUF_t {
69 SD16BUF_0 = 0x0000, /*! Buffer disabled */
70 SD16BUF_1 = 0x2000, /*! Slow speed/current */
71 SD16BUF_2 = 0x4000, /*! Medium speed/current */
72 SD16BUF_3 = 0x6000 /*! High speed/current */
73 };
74
75 /*! SD16UNI Bit */
76 enum SD16UNI_t {
77 SD16UNI_OFF = 0x0000, /*! Bipolar mode */
78 SD16UNI = 0x10000 /*! Unipolar mode */
79 };
80
81 /*! SD16XOSR Bit */
82 enum SD16XOSR_t {
83 SD16XOSR_OFF = 0x000, /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
84 * select the oversampling ratio. See SD16OSRx bit description for settings */
85 SD16XOSR = 0x800 /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
86 * select the oversampling ratio. See SD16OSRx bit description for settings */
87 };
88
89 /*! SD16SNGL Bit */
90 enum SD16SNGL_t {
91 SD16SNGL_OFF = 0x000, /*! Bipolar mode */
92 SD16SNGL = 0x400 /*! Unipolar mode */
93 };
94
95 /*! SD16OSRx Bits */
96 enum SD16OSR_t {
97 SD16OSR_256 = 0x000, /*! SD16XOSR = 0 */
98 SD16OSR_128 = 0x100, /*! SD16XOSR = 0 */
99 SD16OSR_64 = 0x200, /*! SD16XOSR = 0 */
100 SD16OSR_32 = 0x300, /*! SD16XOSR = 0 */
101 SD16OSR_512 = 0x800, /*! SD16XOSR = 1 */
102 SD16OSR_1024 = 0x900 /*! SD16XOSR = 1 */
103 };
104
105 /*! SD16LSBTOG Bit */
106 enum SD16LSBTOG_t {
107 SD16LSBTOG_OFF = 0x00, /*! SD16LSBACC does not toggle with each SD16MEM0 read */
108 SD16LSBTOG = 0x80 /*! SD16LSBACC toggles with each SD16MEM0 read */
109 };
110
111 /*! SD16LSBACC Bit */
112 enum SD16LSBACC_t {
113 SD16LSBACC_OFF = 0x00, /*! SD16MEMx contains the most significant 16-bits of the conversion */
114 SD16LSBACC = 0x40 /*! SD16MEMx contains the least significant 16-bits of the conversion */
115 };
116
117 /*! SD16OVIFG Bit */
118 enum SD16OVIFG_t {
119 SD16OVIFG_OFF = 0x00, /*! No overflow interrupt pending */
120 SD16OVIFG = 0x20 /*! Overflow interrupt pending */
121 };
122
123 /*! SD16DF Bit */
124 enum SD16DF_t {
125 SD16DF_OFF = 0x00, /*! Offset binary */
126 SD16DF = 0x10 /*! 2's complement */
127 };
128
129 /*! SD16IE Bit */
130 enum SD16IE_t {
131 SD16IE_OFF = 0x00, /*! Disabled */
132 SD16IE = 0x08 /*! Enabled */
133 };
134
135 /*! SD16IFG Bit */
136 enum SD16IFG_t {
137 SD16IFG_OFF = 0x00, /*! No interrupt pending */
138 SD16IFG = 0x04 /*! Interrupt pending */
139 };
140
141 /*! SD16SC Bit */
142 enum SD16SC_t {
143 SD16SC_OFF = 0x00, /*! No conversino start */
144 SD16SC = 0x02 /*! Start conversion */
145 };
146
147 /*! SD16INTDLYx Bits */
148 enum SD16INTDLY_t {
149 SD16INTDLY_0 = 0x00, /*! Fourth sample causes interrupt */
150 SD16INTDLY_1 = 0x40, /*! Third sample causes interrupt */
151 SD16INTDLY_2 = 0x80, /*! Second sample causes interrupt */
152 SD16INTDLY_3 = 0xC0 /*! First sample causes interrupt */
153 };
154
155 /*! SD16GAINx Bits */
156 enum SD16GAIN_t {
157 SD16GAIN_1 = 0x00, /*! Multiply by 1 */
158 SD16GAIN_2 = 0x08, /*! Multiply by 2 */
159 SD16GAIN_4 = 0x10, /*! Multiply by 4 */
160 SD16GAIN_8 = 0x18, /*! Multiply by 8 */
161 SD16GAIN_16 = 0x20, /*! Multiply by 16 */
162 SD16GAIN_32 = 0x28 /*! Multiply by 32 */
163 };
164
165 /*! SD16INCHx Bits */
166 enum SD16INCH_t {
167 SD16INCH_0 = 0x000, /*! A0 */
168 SD16INCH_1 = 0x001, /*! A1 */
169 SD16INCH_2 = 0x010, /*! A2 */
170 SD16INCH_3 = 0x011, /*! A3 */
171 SD16INCH_4 = 0x100, /*! A4 */
172 SD16INCH_5 = 0x101, /*! A5 - (AVcc - AVss)/11 */
173 SD16INCH_6 = 0x110, /*! A6 - Temperature Sensor */
174 SD16INCH_7 = 0x111 /*! A7 - Short PGA offset measurement */
175 };
176
177
178 /*! SD16_A Analog Enable Bit 7 */
179 enum SD16AE7_t {
180 SD16AE7_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
181 SD16AE7 = 0x0080 /*! External input enabled */
182 };
183
184 /*! SD16_A Analog Enable Bit 6 */
185 enum SD16AE6_t {
186 SD16AE6_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
187 SD16AE6 = 0x0040 /*! External input enabled */
188 };
189
190 /*! SD16_A Analog Enable Bit 5 */
191 enum SD16AE5_t {
192 SD16AE5_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
193 SD16AE5 = 0x0020 /*! External input enabled */
194 };
195
196 /*! SD16_A Analog Enable Bit 4 */
197 enum SD16AE4_t {
198 SD16AE4_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
199 SD16AE4 = 0x0010 /*! External input enabled */
200 };
201
202 /*! SD16_A Analog Enable Bit 3 */
203 enum SD16AE3_t {
204 SD16AE3_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
205 SD16AE3 = 0x0008 /*! External input enabled */
206 };
207
208 /*! SD16_A Analog Enable Bit 2 */
209 enum SD16AE2_t {
210 SD16AE2_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
211 SD16AE2 = 0x0004 /*! External input enabled */
212 };
213
214 /*! SD16_A Analog Enable Bit 1 */
215 enum SD16AE1_t {
216 SD16AE1_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
217 SD16AE1 = 0x0002 /*! External input enabled */
218 };
219
220 /*! SD16_A Analog Enable Bit 0 */
221 enum SD16AE0_t {
222 SD16AE0_OFF = 0x0000, /*! External input disabled. Negative inputs are internally connected to VSS. */
223 SD16AE0 = 0x0001 /*! External input enabled */
224 };
225
226 /*! SD16_A Interrupt */
227 enum SD16IV_SD16OVIFG_t {
228 SD16IV_SD16OVIFG_OFF = 0x0000, /*! No Interrupt pending */
229 SD16IV_SD16OVIFG = 0x0002 /*! SD16OVIFG */
230 };
231
232 /*! SD16_A SD16MEMx overflow */
233 enum SD16IV_SD16MEM0_t {
234 SD16IV_SD16MEM0_OFF = 0x0000, /*! No Interrupt pending */
235 SD16IV_SD16MEM0 = 0x0004 /*! SD16MEM0 SD16IFG */
236 };
237
238
239 /*!
240 * ======== ForceSetDefaultRegister_t ========
241 * Force Set Default Register
242 *
243 * Type to store if each register needs to be forced initialized
244 * even if the register is in default state.
245 *
246 * @see #ForceSetDefaultRegister_t
247 */
248 struct ForceSetDefaultRegister_t {
249 String register;
250 Bool regForceSet;
251 }
252
253 instance:
254
255 }