1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2008 Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12
13 /*
14 * ======== IMSP430F55xx.xdc ========
15 * Common definitions for MSP430F55xx devices
16 *
17 * This device can load code for different MSP430 ISAs - `MSP430` and
18 * `MSP430X`. The parameter `{@link #isa}` is set to a JavaScript regular
19 * expression that covers different MSP430 ISAs.
20 *
21 *! Revision History
22 *! ================
23 *! 01-Mar-2010 sg Created.
24 */
25
26 metaonly interface IMSP430F55xx inherits IMSP430
27 {
28
29 instance:
30
31 override config string cpuCore = "MSP430X";
32 override config string isa = "430|430X";
33
34 config ti.catalog.msp430.peripherals.special_function.IE1.Instance
35 interruptEnableRegister1;
36 config ti.catalog.msp430.peripherals.timer.Timer0_A5.Instance TA0;
37 config ti.catalog.msp430.peripherals.timer.Timer1_A3.Instance TA1;
38 config ti.catalog.msp430.peripherals.timer.Timer2_A3.Instance TA2;
39 config ti.catalog.msp430.peripherals.timer.Timer0_B7.Instance TB0;
40 config ti.catalog.msp430.peripherals.watchdog.WDTplus.Instance wdtPlus;
41 config ti.catalog.msp430.peripherals.interrupt.Interrupt_Controller.Instance
42 interruptController;
43
44 /*!
45 * ======== commonMap ========
46 * Memory map elements shared by all MSP430F55xx devices
47 */
48 config xdc.platform.IPlatform.Memory commonMap[string] = [
49
50 ["PERIPHERALS", {
51 comment: "Memory mapped peripherals",
52 name: "PERIPHERALS",
53 base: 0x0,
54 len: 0x1000,
55 space: "io",
56 access: "RW"
57 }],
58
59 ["BSL", {
60 comment: "Bootstrap loader (flash)",
61 name: "BSL",
62 base: 0x1000,
63 len: 0x800,
64 space: "code",
65 access: "RW"
66 }],
67
68 ["INFOD", {
69 comment: "Information Memory D (flash)",
70 name: "INFOD",
71 base: 0x1800,
72 len: 0x80,
73 space: "data",
74 access: "RW"
75 }],
76
77 ["INFOC", {
78 comment: "Information Memory C (flash)",
79 name: "INFOC",
80 base: 0x1880,
81 len: 0x80,
82 space: "data",
83 access: "RW"
84 }],
85
86 ["INFOB", {
87 comment: "Information Memory B (flash)",
88 name: "INFOB",
89 base: 0x1900,
90 len: 0x80,
91 space: "data",
92 access: "RW"
93 }],
94
95 ["INFOA", {
96 comment: "Information Memory A (flash)",
97 name: "INFOA",
98 base: 0x1980,
99 len: 0x80,
100 space: "data",
101 access: "RW"
102 }],
103
104 ["INT00", {
105 comment: "Reserved Vector",
106 name: "INT00",
107 base: 0xFF80,
108 len: 0x2,
109 space: "data"
110 }],
111
112 ["INT01", {
113 comment: "Reserved Vector",
114 name: "INT01",
115 base: 0xFF82,
116 len: 0x2,
117 space: "data"
118 }],
119
120 ["INT02", {
121 comment: "Reserved Vector",
122 name: "INT02",
123 base: 0xFF84,
124 len: 0x2,
125 space: "data"
126 }],
127
128 ["INT03", {
129 comment: "Reserved Vector",
130 name: "INT03",
131 base: 0xFF86,
132 len: 0x2,
133 space: "data"
134 }],
135
136 ["INT04", {
137 comment: "Reserved Vector",
138 name: "INT04",
139 base: 0xFF88,
140 len: 0x2,
141 space: "data"
142 }],
143
144 ["INT05", {
145 comment: "Reserved Vector",
146 name: "INT05",
147 base: 0xFF8A,
148 len: 0x2,
149 space: "data"
150 }],
151
152 ["INT06", {
153 comment: "Reserved Vector",
154 name: "INT06",
155 base: 0xFF8C,
156 len: 0x2,
157 space: "data"
158 }],
159
160 ["INT07", {
161 comment: "Reserved Vector",
162 name: "INT07",
163 base: 0xFF8E,
164 len: 0x2,
165 space: "data"
166 }],
167
168 ["INT08", {
169 comment: "Reserved Vector",
170 name: "INT08",
171 base: 0xFF90,
172 len: 0x2,
173 space: "data"
174 }],
175
176 ["INT09", {
177 comment: "Reserved Vector",
178 name: "INT09",
179 base: 0xFF92,
180 len: 0x2,
181 space: "data"
182 }],
183
184 ["INT10", {
185 comment: "Reserved Vector",
186 name: "INT10",
187 base: 0xFF94,
188 len: 0x2,
189 space: "data"
190 }],
191
192 ["INT11", {
193 comment: "Reserved Vector",
194 name: "INT11",
195 base: 0xFF96,
196 len: 0x2,
197 space: "data"
198 }],
199
200 ["INT12", {
201 comment: "Reserved Vector",
202 name: "INT12",
203 base: 0xFF98,
204 len: 0x2,
205 space: "data"
206 }],
207
208 ["INT13", {
209 comment: "Reserved Vector",
210 name: "INT13",
211 base: 0xFF9A,
212 len: 0x2,
213 space: "data"
214 }],
215
216 ["INT14", {
217 comment: "Reserved Vector",
218 name: "INT14",
219 base: 0xFF9C,
220 len: 0x2,
221 space: "data"
222 }],
223
224 ["INT15", {
225 comment: "Reserved Vector",
226 name: "INT15",
227 base: 0xFF9E,
228 len: 0x2,
229 space: "data"
230 }],
231
232 ["INT16", {
233 comment: "Reserved Vector",
234 name: "INT16",
235 base: 0xFFA0,
236 len: 0x2,
237 space: "data"
238 }],
239
240 ["INT17", {
241 comment: "Reserved Vector",
242 name: "INT17",
243 base: 0xFFA2,
244 len: 0x2,
245 space: "data"
246 }],
247
248 ["INT18", {
249 comment: "Reserved Vector",
250 name: "INT18",
251 base: 0xFFA4,
252 len: 0x2,
253 space: "data"
254 }],
255
256 ["INT19", {
257 comment: "Reserved Vector",
258 name: "INT19",
259 base: 0xFFA6,
260 len: 0x2,
261 space: "data"
262 }],
263
264 ["INT20", {
265 comment: "Reserved Vector",
266 name: "INT20",
267 base: 0xFFA8,
268 len: 0x2,
269 space: "data"
270 }],
271
272 ["INT21", {
273 comment: "Reserved Vector",
274 name: "INT21",
275 base: 0xFFAA,
276 len: 0x2,
277 space: "data"
278 }],
279
280 ["INT22", {
281 comment: "Reserved Vector",
282 name: "INT22",
283 base: 0xFFAC,
284 len: 0x2,
285 space: "data"
286 }],
287
288 ["INT23", {
289 comment: "Reserved Vector",
290 name: "INT23",
291 base: 0xFFAE,
292 len: 0x2,
293 space: "data"
294 }],
295
296 ["INT24", {
297 comment: "Reserved Vector",
298 name: "INT24",
299 base: 0xFFB0,
300 len: 0x2,
301 space: "data"
302 }],
303
304 ["INT25", {
305 comment: "Reserved Vector",
306 name: "INT25",
307 base: 0xFFB2,
308 len: 0x2,
309 space: "data"
310 }],
311
312 ["INT26", {
313 comment: "Reserved Vector",
314 name: "INT26",
315 base: 0xFFB4,
316 len: 0x2,
317 space: "data"
318 }],
319
320 ["INT27", {
321 comment: "Reserved Vector",
322 name: "INT27",
323 base: 0xFFB6,
324 len: 0x2,
325 space: "data"
326 }],
327
328 ["INT28", {
329 comment: "Reserved Vector",
330 name: "INT28",
331 base: 0xFFB8,
332 len: 0x2,
333 space: "data"
334 }],
335
336 ["INT29", {
337 comment: "Reserved Vector",
338 name: "INT29",
339 base: 0xFFBA,
340 len: 0x2,
341 space: "data"
342 }],
343
344 ["INT30", {
345 comment: "Reserved Vector",
346 name: "INT30",
347 base: 0xFFBC,
348 len: 0x2,
349 space: "data"
350 }],
351
352 ["INT31", {
353 comment: "Reserved Vector",
354 name: "INT31",
355 base: 0xFFBE,
356 len: 0x2,
357 space: "data"
358 }],
359
360 ["INT32", {
361 comment: "Reserved Vector",
362 name: "INT32",
363 base: 0xFFC0,
364 len: 0x2,
365 space: "data"
366 }],
367
368 ["INT33", {
369 comment: "Reserved Vector",
370 name: "INT33",
371 base: 0xFFC2,
372 len: 0x2,
373 space: "data"
374 }],
375
376 ["INT34", {
377 comment: "Reserved Vector",
378 name: "INT34",
379 base: 0xFFC4,
380 len: 0x2,
381 space: "data"
382 }],
383
384 ["INT35", {
385 comment: "Reserved Vector",
386 name: "INT35",
387 base: 0xFFC6,
388 len: 0x2,
389 space: "data"
390 }],
391
392 ["INT36", {
393 comment: "Reserved Vector",
394 name: "INT36",
395 base: 0xFFC8,
396 len: 0x2,
397 space: "data"
398 }],
399
400 ["INT37", {
401 comment: "Reserved Vector",
402 name: "INT37",
403 base: 0xFFCA,
404 len: 0x2,
405 space: "data"
406 }],
407
408 ["INT38", {
409 comment: "Reserved Vector",
410 name: "INT38",
411 base: 0xFFCC,
412 len: 0x2,
413 space: "data"
414 }],
415
416 ["INT39", {
417 comment: "Reserved Vector",
418 name: "INT39",
419 base: 0xFFCE,
420 len: 0x2,
421 space: "data"
422 }],
423
424 ["INT40", {
425 comment: "Reserved Vector",
426 name: "INT40",
427 base: 0xFFD0,
428 len: 0x2,
429 space: "data"
430 }],
431
432 ["INT41", {
433 comment: "RTC_A Vector",
434 name: "INT41",
435 base: 0xFFD2,
436 len: 0x2,
437 space: "data"
438 }],
439
440 ["INT42", {
441 comment: "I/O Port P2 Vector",
442 name: "INT42",
443 base: 0xFFD4,
444 len: 0x2,
445 space: "data"
446 }],
447
448 ["INT43", {
449 comment: "TA2 CCR1-CCR2 Vector",
450 name: "INT43",
451 base: 0xFFD6,
452 len: 0x2,
453 space: "data"
454 }],
455
456 ["INT44", {
457 comment: "TA2 CCR0 Vector",
458 name: "INT44",
459 base: 0xFFD8,
460 len: 0x2,
461 space: "data"
462 }],
463
464 ["INT45", {
465 comment: "USCI_B1 Receive/Transmit Vector",
466 name: "INT45",
467 base: 0xFFDA,
468 len: 0x2,
469 space: "data"
470 }],
471
472 ["INT46", {
473 comment: "USCI_A1 Receive/Transmit Vector",
474 name: "INT46",
475 base: 0xFFDC,
476 len: 0x2,
477 space: "data"
478 }],
479
480 ["INT47", {
481 comment: "I/O Port P1 Vector",
482 name: "INT47",
483 base: 0xFFDE,
484 len: 0x2,
485 space: "data"
486 }],
487
488 ["INT48", {
489 comment: "TA1 CCR1-CCR2 Vector",
490 name: "INT48",
491 base: 0xFFE0,
492 len: 0x2,
493 space: "data"
494 }],
495
496 ["INT49", {
497 comment: "TA1 CCR0 Vector",
498 name: "INT49",
499 base: 0xFFE2,
500 len: 0x2,
501 space: "data"
502 }],
503
504 ["INT50", {
505 comment: "DMA Vector",
506 name: "INT50",
507 base: 0xFFE4,
508 len: 0x2,
509 space: "data"
510 }],
511
512 ["INT51", {
513 comment: "USB_UBM Vector",
514 name: "INT51",
515 base: 0xFFE6,
516 len: 0x2,
517 space: "data"
518 }],
519
520 ["INT52", {
521 comment: "TA0 CCR1-CCR4 Vector",
522 name: "INT52",
523 base: 0xFFE8,
524 len: 0x2,
525 space: "data"
526 }],
527
528 ["INT53", {
529 comment: "TA0 CCR0 Vector",
530 name: "INT53",
531 base: 0xFFEA,
532 len: 0x2,
533 space: "data"
534 }],
535
536 ["INT54", {
537 comment: "ADC12_A Vector",
538 name: "INT54",
539 base: 0xFFEC,
540 len: 0x2,
541 space: "data"
542 }],
543
544 ["INT55", {
545 comment: "USCI_B0 Receive/Transmit Vector",
546 name: "INT55",
547 base: 0xFFEE,
548 len: 0x2,
549 space: "data"
550 }],
551
552 ["INT56", {
553 comment: "USCI_A0 Receive/Transmit Vector",
554 name: "INT56",
555 base: 0xFFF0,
556 len: 0x2,
557 space: "data"
558 }],
559
560 ["INT57", {
561 comment: "Watchdog Timer_A Interval Timer Mode Vector",
562 name: "INT57",
563 base: 0xFFF2,
564 len: 0x2,
565 space: "data"
566 }],
567
568 ["INT58", {
569 comment: "TB0 CCR1-CCR6 Vector",
570 name: "INT58",
571 base: 0xFFF4,
572 len: 0x2,
573 space: "data"
574 }],
575
576 ["INT59", {
577 comment: "TB0 CCR0 Vector",
578 name: "INT59",
579 base: 0xFFF6,
580 len: 0x2,
581 space: "data"
582 }],
583
584 ["INT60", {
585 comment: "Comp_B Vector",
586 name: "INT60",
587 base: 0xFFF8,
588 len: 0x2,
589 space: "data"
590 }],
591
592 ["INT61", {
593 comment: "User NMI Vector",
594 name: "INT61",
595 base: 0xFFFA,
596 len: 0x2,
597 space: "data"
598 }],
599
600 ["INT62", {
601 comment: "System NMI Vector",
602 name: "INT62",
603 base: 0xFFFC,
604 len: 0x2,
605 space: "data"
606 }],
607
608 ["RESET", {
609 comment: "Reset Vector",
610 name: "RESET",
611 base: 0xFFFE,
612 len: 0x2,
613 space: "data"
614 }],
615 ];
616 }