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13 14 15 16
17
18 package ti.catalog.arm.cortexm3.lm3init;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Stellaris M3 Boot Support.
25 *
26 * The Boot module supports boot initialization for the Stellaris M3 devices.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41
42 metaonly module Boot
43 {
44 metaonly struct ModuleView {
45 Bool configureClock;
46 Bool sysClockDivEnable;
47 String sysClockDiv;
48 Bool pwmClockDivEnable;
49 String pwmClockDiv;
50 String xtal;
51 String oscSrc;
52 Bool pllBypass;
53 Bool pllOutEnable;
54 Bool ioscDisable;
55 Bool moscDisable;
56 Bool configureLdo;
57 String ldoOut;
58 }
59
60 @Facet
61 metaonly config ViewInfo.Instance rovViewInfo =
62 ViewInfo.create({
63 viewMap: [
64 [
65 'Module',
66 {
67 type: ViewInfo.MODULE,
68 viewInitFxn: 'viewInitModule',
69 structName: 'ModuleView'
70 }
71 ],
72 ]
73 });
74
75
76 enum SysDiv {
77 SYSDIV_1 = 0x07800000,
78 SYSDIV_2 = 0x00C00000,
79 SYSDIV_3 = 0x01400000,
80 SYSDIV_4 = 0x01C00000,
81 SYSDIV_5 = 0x02400000,
82 SYSDIV_6 = 0x02C00000,
83 SYSDIV_7 = 0x03400000,
84 SYSDIV_8 = 0x03C00000,
85 SYSDIV_9 = 0x04400000,
86 SYSDIV_10 = 0x04C00000,
87 SYSDIV_11 = 0x05400000,
88 SYSDIV_12 = 0x05C00000,
89 SYSDIV_13 = 0x06400000,
90 SYSDIV_14 = 0x06C00000,
91 SYSDIV_15 = 0x07400000,
92 SYSDIV_16 = 0x07C00000,
93 SYSDIV_17 = 0x88400000,
94 SYSDIV_18 = 0x88C00000,
95 SYSDIV_19 = 0x89400000,
96 SYSDIV_20 = 0x89C00000,
97 SYSDIV_21 = 0x8A400000,
98 SYSDIV_22 = 0x8AC00000,
99 SYSDIV_23 = 0x8B400000,
100 SYSDIV_24 = 0x8BC00000,
101 SYSDIV_25 = 0x8C400000,
102 SYSDIV_26 = 0x8CC00000,
103 SYSDIV_27 = 0x8D400000,
104 SYSDIV_28 = 0x8DC00000,
105 SYSDIV_29 = 0x8E400000,
106 SYSDIV_30 = 0x8EC00000,
107 SYSDIV_31 = 0x8F400000,
108 SYSDIV_32 = 0x8FC00000,
109 SYSDIV_33 = 0x90400000,
110 SYSDIV_34 = 0x90C00000,
111 SYSDIV_35 = 0x91400000,
112 SYSDIV_36 = 0x91C00000,
113 SYSDIV_37 = 0x92400000,
114 SYSDIV_38 = 0x92C00000,
115 SYSDIV_39 = 0x93400000,
116 SYSDIV_40 = 0x93C00000,
117 SYSDIV_41 = 0x94400000,
118 SYSDIV_42 = 0x94C00000,
119 SYSDIV_43 = 0x95400000,
120 SYSDIV_44 = 0x95C00000,
121 SYSDIV_45 = 0x96400000,
122 SYSDIV_46 = 0x96C00000,
123 SYSDIV_47 = 0x97400000,
124 SYSDIV_48 = 0x97C00000,
125 SYSDIV_49 = 0x98400000,
126 SYSDIV_50 = 0x98C00000,
127 SYSDIV_51 = 0x99400000,
128 SYSDIV_52 = 0x99C00000,
129 SYSDIV_53 = 0x9A400000,
130 SYSDIV_54 = 0x9AC00000,
131 SYSDIV_55 = 0x9B400000,
132 SYSDIV_56 = 0x9BC00000,
133 SYSDIV_57 = 0x9C400000,
134 SYSDIV_58 = 0x9CC00000,
135 SYSDIV_59 = 0x9D400000,
136 SYSDIV_60 = 0x9DC00000,
137 SYSDIV_61 = 0x9E400000,
138 SYSDIV_62 = 0x9EC00000,
139 SYSDIV_63 = 0x9F400000,
140 SYSDIV_64 = 0x9FC00000,
141 SYSDIV_2_5 = 0xC1000000,
142 SYSDIV_3_5 = 0xC1800000,
143 SYSDIV_4_5 = 0xC2000000,
144 SYSDIV_5_5 = 0xC2800000,
145 SYSDIV_6_5 = 0xC3000000,
146 SYSDIV_7_5 = 0xC3800000,
147 SYSDIV_8_5 = 0xC4000000,
148 SYSDIV_9_5 = 0xC4800000,
149 SYSDIV_10_5 = 0xC5000000,
150 SYSDIV_11_5 = 0xC5800000,
151 SYSDIV_12_5 = 0xC6000000,
152 SYSDIV_13_5 = 0xC6800000,
153 SYSDIV_14_5 = 0xC7000000,
154 SYSDIV_15_5 = 0xC7800000,
155 SYSDIV_16_5 = 0xC8000000,
156 SYSDIV_17_5 = 0xC8800000,
157 SYSDIV_18_5 = 0xC9000000,
158 SYSDIV_19_5 = 0xC9800000,
159 SYSDIV_20_5 = 0xCA000000,
160 SYSDIV_21_5 = 0xCA800000,
161 SYSDIV_22_5 = 0xCB000000,
162 SYSDIV_23_5 = 0xCB800000,
163 SYSDIV_24_5 = 0xCC000000,
164 SYSDIV_25_5 = 0xCC800000,
165 SYSDIV_26_5 = 0xCD000000,
166 SYSDIV_27_5 = 0xCD800000,
167 SYSDIV_28_5 = 0xCE000000,
168 SYSDIV_29_5 = 0xCE800000,
169 SYSDIV_30_5 = 0xCF000000,
170 SYSDIV_31_5 = 0xCF800000,
171 SYSDIV_32_5 = 0xD0000000,
172 SYSDIV_33_5 = 0xD0800000,
173 SYSDIV_34_5 = 0xD1000000,
174 SYSDIV_35_5 = 0xD1800000,
175 SYSDIV_36_5 = 0xD2000000,
176 SYSDIV_37_5 = 0xD2800000,
177 SYSDIV_38_5 = 0xD3000000,
178 SYSDIV_39_5 = 0xD3800000,
179 SYSDIV_40_5 = 0xD4000000,
180 SYSDIV_41_5 = 0xD4800000,
181 SYSDIV_42_5 = 0xD5000000,
182 SYSDIV_43_5 = 0xD5800000,
183 SYSDIV_44_5 = 0xD6000000,
184 SYSDIV_45_5 = 0xD6800000,
185 SYSDIV_46_5 = 0xD7000000,
186 SYSDIV_47_5 = 0xD7800000,
187 SYSDIV_48_5 = 0xD8000000,
188 SYSDIV_49_5 = 0xD8800000,
189 SYSDIV_50_5 = 0xD9000000,
190 SYSDIV_51_5 = 0xD9800000,
191 SYSDIV_52_5 = 0xDA000000,
192 SYSDIV_53_5 = 0xDA800000,
193 SYSDIV_54_5 = 0xDB000000,
194 SYSDIV_55_5 = 0xDB800000,
195 SYSDIV_56_5 = 0xDC000000,
196 SYSDIV_57_5 = 0xDC800000,
197 SYSDIV_58_5 = 0xDD000000,
198 SYSDIV_59_5 = 0xDD800000,
199 SYSDIV_60_5 = 0xDE000000,
200 SYSDIV_61_5 = 0xDE800000,
201 SYSDIV_62_5 = 0xDF000000,
202 SYSDIV_63_5 = 0xDF800000
203 }
204
205 enum PwmDiv {
206 PWMDIV_1 = 0x00000000,
207 PWMDIV_2 = 0x00100000,
208 PWMDIV_4 = 0x00120000,
209 PWMDIV_8 = 0x00140000,
210 PWMDIV_16 = 0x00160000,
211 PWMDIV_32 = 0x00180000,
212 PWMDIV_64 = 0x001A0000
213 }
214
215 enum XtalFreq {
216 XTAL_1MHZ = 0x00000000,
217 XTAL_1_84MHZ = 0x00000040,
218 XTAL_2MHZ = 0x00000080,
219 XTAL_2_45MHZ = 0x000000C0,
220 XTAL_3_57MHZ = 0x00000100,
221 XTAL_3_68MHZ = 0x00000140,
222 XTAL_4MHZ = 0x00000180,
223 XTAL_4_09MHZ = 0x000001C0,
224 XTAL_4_91MHZ = 0x00000200,
225 XTAL_5MHZ = 0x00000240,
226 XTAL_5_12MHZ = 0x00000280,
227 XTAL_6MHZ = 0x000002C0,
228 XTAL_6_14MHZ = 0x00000300,
229 XTAL_7_37MHZ = 0x00000340,
230 XTAL_8MHZ = 0x00000380,
231 XTAL_8_19MHZ = 0x000003C0,
232 XTAL_10MHZ = 0x00000400,
233 XTAL_12MHZ = 0x00000440,
234 XTAL_12_2MHZ = 0x00000480,
235 XTAL_13_5MHZ = 0x000004C0,
236 XTAL_14_3MHZ = 0x00000500,
237 XTAL_16MHZ = 0x00000540,
238 XTAL_16_3MHZ = 0x00000580
239 }
240
241 enum OscSrc {
242 OSCSRC_MAIN = 0x00000000,
243 OSCSRC_INT = 0x00000010,
244 OSCSRC_INT4 = 0x00000020,
245 OSCSRC_30 = 0x00000030
246 }
247
248 enum LdoOut {
249 LDOPCTL_2_55V = 0x0000001F,
250 LDOPCTL_2_60V = 0x0000001E,
251 LDOPCTL_2_65V = 0x0000001D,
252 LDOPCTL_2_70V = 0x0000001C,
253 LDOPCTL_2_75V = 0x0000001B,
254 LDOPCTL_2_25V = 0x00000005,
255 LDOPCTL_2_30V = 0x00000004,
256 LDOPCTL_2_35V = 0x00000003,
257 LDOPCTL_2_40V = 0x00000002,
258 LDOPCTL_2_45V = 0x00000001,
259 LDOPCTL_2_50V = 0x00000000
260 }
261
262 /*!
263 * Clock configuration flag, default is false.
264 *
265 * Set to true to automatically configure the Clock.
266 */
267 config Bool configureClock = false;
268
269 /*! SYS Clock Divisor */
270 config SysDiv sysClockDiv = SYSDIV_1;
271
272 /*! PWM Clock Divisor */
273 config PwmDiv pwmClockDiv = PWMDIV_1;
274
275 /*! Crystal Value */
276 config XtalFreq xtal = XTAL_1MHZ;
277
278 /*! Oscillator Source */
279 config OscSrc oscSrc = OSCSRC_MAIN;
280
281 /*! PLL Bypass flag */
282 config Bool pllBypass = false;
283
284 /*! PLL Output Enable flag */
285 config Bool pllOutEnable = false;
286
287 /*! Internal Oscillator Disable flag */
288 config Bool ioscDisable = false;
289
290 /*! Main Oscillator Disable flag */
291 config Bool moscDisable = false;
292
293 /*!
294 * LDO configuration flag, default is false.
295 *
296 * Set to true to automatically configure the LDO.
297 */
298 config Bool configureLdo = false;
299
300 /*!
301 * LDO VADJ setting, default is 2.5V
302 */
303 config LdoOut ldoOut = LDOPCTL_2_50V;
304
305 /*!
306 * @_nodoc
307 * computed RCC value based on settings
308 */
309 config UInt ulConfig;
310 };
311 312 313
314