1 /*!
2 * ======== Flash_2xx ========
3 * MSP430 Flash 2xx
4 */
5 metaonlymodule Flash_2xx inherits IFlash {
6
7 /* FCTL1 Register */
8 struct FCTL1_t {
9 FWKEY_t FWKEY; /*! FCTLx password */
10 BLKWRT_t BLKWRT; /*! Block write mode */
11 WRT_t WRT; /*! Write */
12 EEIEX_t EEIEX; /*! Enable Emergency Interrupt Exit */
13 EEI_t EEI; /*! Enable Erase Interrupts */
14 MERAS_t MERAS; /*! Mass erase */
15 ERASE_t ERASE; /*! Erase */
16 }
17
18 /* FCTL2 Register */
19 struct FCTL2_t {
20 FWKEY_t FWKEY; /*! FCTLx password */
21 FSSEL_t FSSEL; /*! Flash controller clock source select */
22 FN5_t FN5; /*! Flash controller clock divider bit 5 */
23 FN4_t FN4; /*! Flash controller clock divider bit 4 */
24 FN3_t FN3; /*! Flash controller clock divider bit 3 */
25 FN3_t FN2; /*! Flash controller clock divider bit 2 */
26 FN1_t FN1; /*! Flash controller clock divider bit 1 */
27 FN0_t FN0; /*! Flash controller clock divider bit 0 */
28 }
29
30 /* FCTL3 Register */
31 struct FCTL3_t {
32 FWKEY_t FWKEY; /*! FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC
33 * will be generated. */
34 FAIL_t FAIL; /*! FAIL Bit 7 Operation failure. This bit is set if the fFTG clock source fails, or a flash
35 * operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset
36 * with software.
37 * 0 No failure
38 * 1 Failure */
39 LOCKA_t LOCKA; /*! SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has
40 * no effect.
41 * 0 Segment A unlocked and all information memory is erased during a
42 * mass erase.
43 * 1 Segment A locked and all information memory is protected from erasure
44 * during a mass erase. */
45 EMEX_t EMEX; /*! Emergency exit
46 * 0 No emergency exit
47 * 1 Emergency exit */
48 LOCK_t LOCK; /*! Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit
49 * can be set anytime during a byte/word write or erase operation and the
50 * operation will complete normally. In the block write mode if the LOCK bit is set
51 * while BLKWRT=WAIT=1, then BLKWRT and WAIT are reset and the mode
52 * ends normally.
53 * 0 Unlocked
54 * 1 Locked */
55 WAIT_t WAIT; /*! Wait. Indicates the flash memory is being written to.
56 * 0 The flash memory is not ready for the next byte/word write
57 * 1 The flash memory is ready for the next byte/word write */
58 ACCVIFG_t ACCVIFG; /*! Access violation interrupt flag
59 * 0 No interrupt pending
60 * 1 Interrupt pending */
61 KEYV_t KEYV; /*! Flash security key violation. This bit indicates an incorrect FCTLx password
62 * was written to any flash control register and generates a PUC when set. KEYV
63 * must be reset with software.
64 * 0 FCTLx password was written correctly
65 * 1 FCTLx password was written incorrectly */
66 BUSY_t BUSY; /*! Busy. This bit indicates the status of the flash timing generator.
67 * 0 Not Busy
68 * 1 Busy */
69 }
70
71 instance:
72 /*! Flash Memory Control Register 1 */
73 config FCTL1_t FCTL1 = {
74 FWKEY : FWKEY,
75 BLKWRT : BLKWRT_OFF,
76 WRT : WRT_OFF,
77 EEIEX : EEIEX_OFF,
78 EEI : EEI_OFF,
79 MERAS : MERAS_OFF,
80 ERASE : ERASE_OFF
81 };
82
83 /*! Determine if each Register needs to be forced set or not */
84 readonlyconfig ForceSetDefaultRegister_t forceSetDefaultRegister[] =
85 [
86 { register : "FCTL1" , regForceSet : false }
87 ];
88 }