1    /*
     2     *  Copyright (c) 2011 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITI8168.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITI8168 ========
    20     *  An interface implemented by all TI8168 devices
    21     *
    22     *  This interface is defined to factor common data about all TI8168 type devices
    23     *  into a single place; they all have the same internal memory.
    24     */
    25    metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet
    26    {
    27    instance:
    28        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    29        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
    30        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
    31    
    32        override config string cpuCore           = "v7A";
    33        override config string isa               = "v7A";
    34        override config string cpuCoreRevision   = "1.0";
    35        override config int    minProgUnitSize   = 1;
    36        override config int    minDataUnitSize   = 1;
    37        override config int    dataWordSize      = 4;
    38    
    39        /*!
    40         *  ======== memMap ========
    41         *  The memory map returned be getMemoryMap().
    42         */
    43        config xdc.platform.IPlatform.Memory memMap[string]  = [
    44            ["SRAM", {
    45                comment:    "On-Chip SRAM",
    46                name:       "SRAM",
    47                base:       0x402F0000,
    48                len:        0x00010000,
    49                space:      "code/data",
    50                access:     "RWX"
    51            }],
    52        
    53            /* 
    54             * OCMC (On-chip RAM) Bank 0
    55             * Size is 128K
    56             */
    57            ["OCMC_0", {
    58                name: "OCMC_0",
    59                base: 0x40300000, 
    60                len:  0x00020000
    61            }],
    62            
    63            /* 
    64             * OCMC (On-chip RAM) Bank 1
    65             * Size is 128K
    66             */
    67            ["OCMC_1", {
    68                name: "OCMC_1",
    69                base: 0x40400000, 
    70                len:  0x00020000
    71            }],
    72    
    73        ];
    74    }
    75    /*
    76     *  @(#) ti.catalog.arm.cortexa8; 1, 0, 0,60; 1-17-2011 09:01:32; /db/ztree/library/trees/platform/platform-l32x/src/
    77     */
    78