1 import ti.catalog.msp430.peripherals.clock.IClock;
2
3 /*!
4 * ======== IFlash ========
5 * MSP430 IFlash interface
6 */
7 metaonly interface IFlash inherits xdc.platform.IPeripheral {
8
9 enum FWKEY_t {
10 FWKEY_OFF = 0x00,
11 FWKEY = 0xA500
12 };
13
14 /*! Block write mode */
15 enum BLKWRT_t {
16 BLKWRT_OFF = (0x0000),
17 BLKWRT = (0x0080)
18 };
19
20 /*! Write */
21 enum WRT_t {
22 WRT_OFF = (0x0000),
23 WRT = 0x0040
24 };
25
26 /*! Enable Emergency Interrupt Exit */
27 enum EEIEX_t {
28 EEIEX_OFF = (0x0000),
29 EEIEX = 0x0010
30 };
31
32 /*! Enable Erase Interrupts */
33 enum EEI_t {
34 EEI_OFF = (0x0000),
35 EEI = 0x0008
36 };
37
38 /*! Mass erase */
39 enum MERAS_t {
40 MERAS_OFF = (0x0000),
41 MERAS = 0x0004
42 };
43
44 /*! Erase */
45 enum ERASE_t {
46 ERASE_OFF = (0x0000),
47 ERASE = 0x0002
48 };
49
50 enum FSSEL_t {
51 FSSEL_0 = 0x0000, /*! ACLK */
52 FSSEL_1 = 0x0040, /*! MCLK */
53 FSSEL_2 = 0x0080, /*! SMCLK */
54 FSSEL_3 = 0x00C0 /*! SMCLK */
55 };
56
57 /*! Flash controller clock divider bit 0 */
58 enum FN0_t {
59 FN0_OFF = (0x0000),
60 FN0 = 0x0001
61 };
62
63 /*! Flash controller clock divider bit 1 */
64 enum FN1_t {
65 FN1_OFF = (0x0000),
66 FN1 = 0x0002
67 };
68
69 /*! Flash controller clock divider bit 2 */
70 enum FN2_t {
71 FN2_OFF = (0x0000),
72 FN2 = 0x0004
73 };
74
75 /*! Flash controller clock divider bit 3 */
76 enum FN3_t {
77 FN3_OFF = (0x0000),
78 FN3 = 0x0008
79 };
80
81 /*! Flash controller clock divider bit 4 */
82 enum FN4_t {
83 FN4_OFF = (0x0000),
84 FN4 = 0x0010
85 };
86
87 /*! Flash controller clock divider bit 5 */
88 enum FN5_t {
89 FN5_OFF = (0x0000),
90 FN5 = 0x0020
91 };
92
93 /*! Operation failure */
94 enum FAIL_t {
95 FAIL_OFF = (0x0000),
96 FAIL = 0x0080
97 };
98
99 /*! SegmentA and Info lock */
100 enum LOCKA_t {
101 LOCKA_OFF = (0x0000),
102 LOCKA = 0x0040
103 };
104
105 /*! Emergency exit */
106 enum EMEX_t {
107 EMEX_OFF = (0x0000),
108 EMEX = 0x0020
109 };
110
111 /*! Lock */
112 enum LOCK_t {
113 LOCK_OFF = (0x0000),
114 LOCK = 0x0010
115 };
116
117 /*! Wait */
118 enum WAIT_t {
119 WAIT_OFF = (0x0000),
120 WAIT = 0x0008
121 };
122
123 /*! Access violation interrupt flag */
124 enum ACCVIFG_t {
125 ACCVIFG_OFF = (0x0000),
126 ACCVIFG = 0x0004
127 };
128
129 /*! Flash security key violation */
130 enum KEYV_t {
131 KEYV_OFF = (0x0000),
132 KEYV = 0x0002
133 };
134
135 /*! Busy */
136 enum BUSY_t {
137 BUSY_OFF = (0x0000),
138 BUSY = 0x0001
139 };
140
141 /*!
142 * ======== ForceSetDefaultRegister_t ========
143 * Force Set Default Register
144 *
145 * Type to store if each register needs to be forced initialized
146 * even if the register is in default state.
147 *
148 * @see #ForceSetDefaultRegister_t
149 */
150 struct ForceSetDefaultRegister_t {
151 String register;
152 Bool regForceSet;
153 }
154
155 create(IClock.Instance clock);
156
157 instance:
158 /*!
159 * ======== baseAddr ========
160 * Address of the peripheral's control register.
161 *
162 * A peripheral's registers are commonly accessed through a structure
163 * that defines the offsets of a particular register from the lowest
164 * address mapped to a peripheral. That lowest address is specified by
165 * this parameter.
166 */
167 config UInt baseAddr;
168
169 /*!
170 * ======== intNum ========
171 * Interrupt source number
172 *
173 */
174 config UInt intNum;
175
176 /*! @_nodoc */
177 config IClock.Instance clock;
178 }