1    /*
     2     *  Copyright (c) 2011 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITI8168.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITI8168 ========
    20     *  An interface implemented by all TI8168 devices
    21     *
    22     *  This interface is defined to factor common data about all TI8168 type devices
    23     *  into a single place; they all have the same internal memory.
    24     */
    25    metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet
    26    {
    27    instance:
    28        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    29        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
    30        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
    31    
    32        override config string cpuCore           = "CM3";
    33        override config string isa               = "v7M";
    34        override config string cpuCoreRevision   = "1.0";
    35        override config int    minProgUnitSize   = 1;
    36        override config int    minDataUnitSize   = 1;
    37        override config int    dataWordSize      = 4;
    38    
    39        /*!
    40         *  ======== memMap ========
    41         *  The memory map returned be getMemoryMap().
    42         */
    43        config xdc.platform.IPlatform.Memory memMap[string] = [
    44    
    45            /* 
    46             * AMMU mapped L2 ROM virtual address
    47             * Physical address is 0x55000000
    48             */
    49            ["L2_ROM", {
    50                name: "L2_ROM",
    51                base: 0x00000000,
    52                len:  0x00004000
    53            }],
    54    
    55            /* 
    56             * AMMU mapped L2 RAM virtual address
    57             * Physical address is 0x55020000
    58             * Size is 256K
    59             */
    60            ["L2_RAM", {
    61                name: "L2_RAM",
    62                base: 0x20000000, 
    63                len:  0x00040000
    64            }],
    65            
    66            /* 
    67             * OCMC (On-chip RAM) Bank 0
    68             * Physical address is 0x40300000
    69             * Size is 128K
    70             */
    71            ["OCMC_0", {
    72                name: "OCMC_0",
    73                base: 0x00300000, 
    74                len:  0x00020000
    75            }],
    76            
    77            /* 
    78             * OCMC (On-chip RAM) Bank 1
    79             * Physical address is 0x40400000
    80             * Size is 128K
    81             */
    82            ["OCMC_0", {
    83                name: "OCMC_0",
    84                base: 0x00400000, 
    85                len:  0x00020000
    86            }],
    87        ];
    88    };
    89    /*
    90     *  @(#) ti.catalog.arm.cortexm3; 1, 0, 0,60; 1-17-2011 09:01:34; /db/ztree/library/trees/platform/platform-l32x/src/
    91     */
    92