1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== TNETV107X.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== TNETV107X ========
21 */
22 metaonly module TNETV107X inherits ti.catalog.ICpuDataSheet
23 {
24
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x00000],
35 ["32k", 0x08000],
36 ["64k", 0x10000],
37 ["128k", 0x20000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',
42 {desc: "L1P Cache",
43 base: 0x11E08000,
44 map: [["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000]],
49 defaultValue: "32k",
50 memorySection: "L1PSRAM"}
51 ],
52
53 ['l1DMode',
54 {desc: "L1D Cache",
55 base: 0x11F04000,
56 map: [["0k", 0x0000],
57 ["4k", 0x1000],
58 ["8k", 0x2000],
59 ["16k", 0x4000],
60 ["32k", 0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}
63 ],
64
65 ['l2Mode',
66 {desc: "L2 Cache",
67 base: 0x11800000,
68 map: [["0k", 0x0000],
69 ["32k", 0x8000],
70 ["64k", 0x10000],
71 ["128k", 0x20000]],
72 defaultValue: "0k",
73 memorySection: "L2RAM"}
74 ],
75
76 ];
77
78 instance:
79 override config int minProgUnitSize = 1;
80 override config int minDataUnitSize = 1;
81 override config int dataWordSize = 4;
82
83 override config string cpuCore = "64x+";
84 override config string isa = "64P";
85
86 config xdc.platform.IPlatform.Memory memMap[string] = [
87 ["L2RAM", {
88 comment: "Internal 128KB L2 memory",
89 name: "L2RAM",
90 base: 0x11800000,
91 len: 0x00020000,
92 space: "code/data",
93 access: "RWX"
94 }],
95
96 ["L1PSRAM", {
97 comment: "Internal 32KB L1 program memory",
98 name: "L1PSRAM",
99 base: 0x11E08000,
100 len: 0x00008000,
101 space: "code",
102 access: "RWX"
103 }],
104
105 ["L1DSRAM", {
106 comment: "Internal 80KB L1 data memory",
107 name: "L1DSRAM",
108 base: 0x11F04000,
109 len: 0x00014000,
110 space: "data",
111 access: "RW"
112 }],
113 ];
114 };
115 /*
116 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:09; /db/ztree/library/trees/platform/platform-l29x/src/
117 */
118