1    /*
     2     *  Copyright (c) 2010 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== TMS320CDRA447.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== TMS320CDRA447 ========
    20     *  The DRA447 device data sheet module.
    21     *
    22     *  This module implements the xdc.platform.ICpuDataSheet interface and is 
    23     *  used by platforms to obtain "data sheet" information about this device.
    24     */
    25    metaonly module TMS320CDRA447 inherits ITMS320CDRA44x
    26    {
    27    
    28        override config long cacheSizeL2[string] = [
    29            ["0k",  0x00000],
    30            ["32k", 0x08000],
    31            ["64k", 0x10000],
    32            ["128k", 0x20000]
    33        ];
    34    
    35        override readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    36                 ['l1PMode',{desc:"L1P Cache",
    37                             base: 0x11E08000,
    38                             map : [["0k",0x0000],
    39                                    ["4k",0x1000],
    40                                    ["8k",0x2000],
    41                                    ["16k",0x4000],
    42                                    ["32k",0x8000]],
    43                             defaultValue: "32k",
    44                             memorySection: "L1PSRAM"}],
    45             
    46                     ['l1DMode',{desc:"L1D Cache",
    47                             base: 0x11F04000,
    48                             map : [["0k",0x0000],
    49                                    ["4k",0x1000],
    50                                    ["8k",0x2000],
    51                                    ["16k",0x4000],
    52                                    ["32k",0x8000]],
    53                             defaultValue: "32k",
    54                             memorySection: "L1DSRAM"}],
    55                         
    56                 ['l2Mode',{desc:"L2 Cache",
    57                             base: 0x11800000,
    58                             map : [["0k",0x0000],
    59                                    ["32k",0x8000],
    60                                    ["64k",0x10000],
    61                                    ],
    62                             defaultValue: "0k",
    63                             memorySection: "IRAM"}], 
    64    
    65        ];
    66    
    67    instance:
    68    
    69        /*!
    70         *  ======== memMap ========
    71         *  The default memory map for this device
    72         */
    73        override config xdc.platform.IPlatform.Memory memMap[string] = [
    74            ["IRAM", {
    75                comment:    "Internal 128KB UMAP0 memory",
    76                name:       "IRAM",
    77                base:       0x11800000,
    78                len:        0x00020000,
    79                space:      "code/data",
    80                access:     "RWX"
    81            }],
    82            
    83            ["L1PSRAM", {
    84                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    85                name:       "L1PSRAM",
    86                base:       0x11E08000,
    87                len:        0x00008000,
    88                space:      "code",
    89                access:     "RWX"
    90            }],
    91    
    92            ["L1DSRAM", {
    93                comment:    "Internal 80KB RAM/CACHE L1 data memory",
    94                name:       "L1DSRAM",
    95                base:       0x11F04000,
    96                len:        0x00014000,
    97                space:      "data",
    98                access:     "RW"
    99            }],
   100    
   101            ["ARM_RAM", {
   102                comment:    "Internal ARM RAM memory",
   103                name:       "ARM_RAM",
   104                base:       0x10008000,
   105                len:        0x00004000,
   106                space:      "data",
   107                access:     "RW"
   108            }],
   109        ];
   110    
   111    };
   112    /*
   113     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:08; /db/ztree/library/trees/platform/platform-l29x/src/
   114     */
   115