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17
18 package ti.catalog.c6000;
19
20 /*!
21 * ======== TMS320CDM6431 ========
22 * The DM6431 device data sheet module.
23 *
24 * This module implements the xdc.platform.ICpuDataSheet interface and is
25 * used by platforms to obtain "data sheet" information about this device.
26 */
27 metaonly module TMS320CDM6431 inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000]
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base: 0x10E08000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base: 0x10F10000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base: 0x10810000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000]],
69 defaultValue: "0k",
70 memorySection: "IRAM"}],
71 ];
72
73 instance:
74
75 override config string cpuCore = "64x+";
76 override config string isa = "64P";
77 override config string cpuCoreRevision = "1.0";
78
79 override config int minProgUnitSize = 1;
80 override config int minDataUnitSize = 1;
81 override config int dataWordSize = 4;
82
83 /*!
84 * ======== memMap ========
85 * The default memory map for this device
86 */
87 config xdc.platform.IPlatform.Memory memMap[string] = [
88 ["IRAM", {
89 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
90 name: "IRAM",
91 base: 0x10810000,
92 len: 0x00010000,
93 space: "code/data",
94 access: "RWX"
95 }],
96
97 ["L1PSRAM", {
98 comment: "Internal 32KB RAM/CACHE L1 program memory",
99 name: "L1PSRAM",
100 base: 0x10E08000,
101 len: 0x00008000,
102 space: "code",
103 access: "RWX"
104 }],
105
106 ["L1DSRAM", {
107 comment: "Internal 32KB RAM/CACHE L1 data memory",
108 name: "L1DSRAM",
109 base: 0x10F10000,
110 len: 0x00008000,
111 space: "data",
112 access: "RW"
113 }],
114 ];
115 };
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119