1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== TMS320C6421.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 /*!
21 * ======== TMS320C6421 ========
22 * The C6421 device data sheet module.
23 *
24 * This module implements the xdc.platform.ICpuDataSheet interface and is
25 * used by platforms to obtain "data sheet" information about this device.
26 */
27 metaonly module TMS320C6421 inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x4000]
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base: 0x10E0C000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base: 0x10F0C000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base: 0x10810000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000]],
69 defaultValue: "0k",
70 memorySection: "IRAM"}],
71
72 ];
73
74 instance:
75
76 override config string cpuCore = "64x+";
77 override config string isa = "64P";
78 override config string cpuCoreRevision = "1.0";
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 /*!
85 * ======== memMap ========
86 * The default memory map for this device
87 */
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89 ["IRAM", {
90 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
91 name: "IRAM",
92 base: 0x10810000,
93 len: 0x00010000,
94 space: "code/data",
95 access: "RWX"
96 }],
97
98 ["L1PSRAM", {
99 comment: "Internal 16KB RAM/CACHE L1 program memory",
100 name: "L1PSRAM",
101 base: 0x10E0C000,
102 len: 0x00004000,
103 space: "code",
104 access: "RWX"
105 }],
106
107 ["L1DSRAM", {
108 comment: "Internal 48KB RAM/CACHE L1 data memory",
109 name: "L1DSRAM",
110 base: 0x10F0C000,
111 len: 0x0000C000,
112 space: "data",
113 access: "RW"
114 }],
115 ];
116 };
117 /*
118 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:04; /db/ztree/library/trees/platform/platform-l29x/src/
119 */
120