1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320DA8xx.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320DA8xx ========
21 * An interface implemented by TMS320DA8xx devices.
22 *
23 */
24 metaonly interface ITMS320DA8xx inherits ti.catalog.ICpuDataSheet
25 {
26
27 config long cacheSizeL1[string] = [
28 ["0k", 0x0000],
29 ["4k", 0x1000],
30 ["8k", 0x2000],
31 ["16k", 0x4000],
32 ["32k", 0x8000],
33 ];
34
35 config long cacheSizeL2[string] = [
36 ["0k", 0x00000],
37 ["32k", 0x08000],
38 ["64k", 0x10000],
39 ["128k",0x20000],
40 ["256k",0x40000],
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base: 0x11E00000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base: 0x11F00000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base: 0x11800000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000],
69 ["128k",0x20000],
70 ["256k",0x40000]],
71 defaultValue: "0k",
72 memorySection: "IRAM"}],
73
74 ];
75
76 instance:
77 override config int minProgUnitSize = 1;
78 override config int minDataUnitSize = 1;
79 override config int dataWordSize = 4;
80
81 override config string cpuCore = "C674";
82 override config string isa = "674";
83 override config string cpuCoreRevision = "1.0";
84
85 config xdc.platform.IPlatform.Memory memMap[string] = [
86 ["IROM", {
87 comment: "Internal 1MB L2 ROM",
88 name: "IROM",
89 base: 0x11700000,
90 len: 0x00100000,
91 space: "code/data",
92 access: "RX"
93 }],
94
95 ["IRAM", {
96 comment: "Internal 256KB L2 memory",
97 name: "IRAM",
98 base: 0x11800000,
99 len: 0x00040000,
100 space: "code/data",
101 access: "RWX"
102 }],
103
104 ["L1PSRAM", {
105 comment: "Internal 32KB L1 program memory",
106 name: "L1PSRAM",
107 base: 0x11E00000,
108 len: 0x00008000,
109 space: "code",
110 access: "RWX"
111 }],
112
113 ["L1DSRAM", {
114 comment: "Internal 32KB L1 data memory",
115 name: "L1DSRAM",
116 base: 0x11F00000,
117 len: 0x00008000,
118 space: "data",
119 access: "RW"
120 }],
121
122 ["L3_CBA_RAM", {
123 comment: "128KB ARM/DSP local shared RAM",
124 name: "L3_CBA_RAM",
125 base: 0x80000000,
126 len: 0x00020000,
127 space: "code/data",
128 access: "RWX"
129 }],
130 ];
131 };
132 /*
133 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:02; /db/ztree/library/trees/platform/platform-l29x/src/
134 */
135