1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CTCI648x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CTCI648x ========
20 * An interface implemented by TCI6487 and TCI6488 devices
21 *
22 * This interface is defined to factor common data about TCI6487 and TCI6488
23 * devices into a single place; they are all the same from the configuration
24 * point of view.
25 */
26 metaonly interface ITMS320CTCI648x inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ["256k", 0x40000]
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 base: 0xE00000,
48 map : [["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]],
53 defaultValue: "32k",
54 memorySection: "L1PSRAM"}],
55
56 ['l1DMode',{desc:"L1D Cache",
57 base: 0xF00000,
58 map : [["0k",0x0000],
59 ["4k",0x1000],
60 ["8k",0x2000],
61 ["16k",0x4000],
62 ["32k",0x8000]],
63 defaultValue: "32k",
64 memorySection: "L1DSRAM"}],
65
66 ['l2Mode',{desc:"L2 Cache",
67 base: 0x00800000,
68 map : [["0k",0x0000],
69 ["32k",0x8000],
70 ["64k",0x10000],
71 ["128k",0x20000],
72 ["256k",0x40000]],
73 defaultValue: "0k",
74 memorySection: "L2RAM"}]
75
76 ];
77
78 config xdc.platform.IPlatform.Memory memBlock[string] = [
79 ["ASYMGEM0L2RAM", {
80 comment: "1536K L2 RAM/CACHE memory",
81 name: "L2RAM",
82 base: 0x00800000,
83 len: 0x00180000,
84 space: "code/data",
85 access: "RWX"
86 }],
87
88 ["ASYMGEM1L2RAM", {
89 comment: "1024K L2 RAM/CACHE memory",
90 name: "L2RAM",
91 base: 0x00800000,
92 len: 0x00100000,
93 space: "code/data",
94 access: "RWX"
95 }],
96
97 ["ASYMGEM2L2RAM", {
98 comment: "512K L2 RAM/CACHE memory",
99 name: "L2RAM",
100 base: 0x00800000,
101 len: 0x00080000,
102 space: "code/data",
103 access: "RWX"
104 }],
105
106 ["SYMGEML2RAM", {
107 comment: "1024K L2 RAM/CACHE memory",
108 name: "L2RAM",
109 base: 0x00800000,
110 len: 0x00100000,
111 space: "code/data",
112 access: "RWX"
113 }],
114
115 ];
116
117 instance:
118
119 override config string cpuCore = "64x+";
120 override config string isa = "64P";
121 override config string cpuCoreRevision = "1.0";
122
123 override config int minProgUnitSize = 1;
124 override config int minDataUnitSize = 1;
125 override config int dataWordSize = 4;
126
127 /*!
128 * ======== memMap ========
129 * The default memory map for this device
130 */
131 config xdc.platform.IPlatform.Memory memMap[string] = [
132
133 ["L1PSRAM", {
134 comment: "Internal 32KB RAM/CACHE L1 program memory",
135 name: "L1PSRAM",
136 base: 0xE00000,
137 len: 0x008000,
138 space: "code",
139 access: "RWX"
140 }],
141
142 ["L1DSRAM", {
143 comment: "Internal 32KB RAM/CACHE L1 data memory",
144 name: "L1DSRAM",
145 base: 0xF00000,
146 len: 0x008000,
147 space: "data",
148 access: "RW"
149 }],
150 ];
151
152 };
153 /*
154 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:01; /db/ztree/library/trees/platform/platform-l29x/src/
155 */
156